" Energy-Efficient Computing"related to papers

Abstract:Aiming at the problems of Uyghur face recognition effect of non-uniform illumination jamming,through the research of sparse representation of traditional methods and Uyghur face complex lighting problems,this paper proposed the method of Uyghur face analysis based on sparse representation combined with partial differential equations to improve Retinex algorithm. The methods improve the Retinex method by partial differential equations, can effectively reduce the Halo phenomenon in reflection coefficient diagram, and get the atoms to light does not change. Then sparse representations is used to realize Uyghur people face recognition in non-uniform lighting. Experiments show that this method an effectively improve the sparse representation method in dealing with complex lighting Uyghur face image recognition,and achieve robustness and high goals.

Abstract:Recently, data classification techniques have been used to solve many problems. As one of the most popular classification algorithms, K-Nearest Neighbor(KNN) algorithm has been widely used. Over the past 50 years, many efforts about parallel computing have been made to improve the efficiency of KNN. A new CUDA-based parallel implementation of KNN algorithm called CUKNN has proved that the parallel solution implemented by GPU is dozens of times faster than the serial solution implemented by CPU. However, plenty of redundant computation has been done in CUKNN. This paper proposes a new parallel solution of KNN algorithm which is implemented by parallel bubble sort. Then we evaluate it on GPU-based heterogeneous computing system using OpenCL, and the result shows that the efficiency of our solution has improved 16 times.

Abstract:High performance graphics generation circuit is required due to higher resolution and more complicated display content of the cockpit display system. A method about graphics generation circuit based on double processor is proposed in this paper. Hardware platform is designed based on two chip of DSP in cooperation with FPGA and SDRAM frame buffer. Graphics generation task is distributed by the main DSP and the result of task distribution is sent to the secondary DSP through linkport. Graphics generation algorithms are performed by the two DSP. The data produced by the secondary DSP is sent to the main DSP by linkport. The graphics data is written to the SDRAM frame buffer by the main DSP. The graphics can be generated and display by ping-pong operation on SDRAM cooperated with FPGA. Experiments show that the efficiency of the graphics generation can be increased by 53% in condition of the power increased by 15%.The EFIS display with 1 024×768 resolution can be generated and the frame rate is 86 f/s.

Abstract:The development of on-chip multiprocessor systems leads to sharp increase in the area of on-chip cache, and its corresponding leakage power has also increased. Cache line in this article are divided into 3 parts to control while the data access section is divided into metadata access and data access in two parts, each supports a variety of modes to control. The operating mode switching to control the cache into three parts enables us to reduce leakage power consumption on average by 76.78%, but the loss of the performance is up to 7.74%. Due to the large loss of performance, this paper describes an improved method of cache decay to optimize control strategies. This strategy not only losses below 3% performance but also ensures optimization of average energy consumption to nearly 75%.