Abstract： NTN is an important technological direction for extending mobile communications from terrestrial coverage to global ubiquitous connectivity, and also a critical foundation for building satellite-terrestrial integrated networks in 6G. By adapting the existing cellular system to long propagation delays, Doppler shifts, random access, and mobility, 5G NTN has achieved integrated access between satellite communications and mobile communications, and is continuously evolving from basic access toward enhanced network capabilities. For 6G, with the development of large-scale LEO constellations, inter-satellite links, regenerative payloads, and on-board intelligence, the research focus of NTN will gradually shift from "satellites adapting to cellular networks" toward "collaborative design of space and terrestrial networks". This paper reviews the technology and standard evolution of 5G NTN, analyzes its technological evolution toward 6G satellite-terrestrial integration from five dimensions—network architecture, air interface technologies, mobility management, multi-satellite networking and resource coordination, and network capabilities—further summarizes the development directions and key technical challenges of 6G satellite-terrestrial integration, and provides an outlook on future unified space-terrestrial networks and spatial information infrastructure integrating communication, sensing, computing, and intelligence.

Abstract：In low‑Earth orbit (LEO) satellite communications for non‑terrestrial networks (NTN),the user equipment shall continuously update the propagation delay and Doppler frequency offset of the serving link according to satellite‑broadcast ephemeris to realize satellite‑ground time‑frequency synchronization. Conventional approaches solve Kepler's equation and execute coordinate transformation time‑slot by time‑slot, resulting in substantial redundant computations, which makes them poorly suited for satellite communication terminals constrained by computing capacity and power consumption. To tackle this problem, this paper presents a calculation method for time‑frequency synchronization parameters, which comprises pre‑computation of common orbital quantities, accurate propagation computation at anchor time‑slots, and interval‑based linear interpolation. Analytical results show that the proposed algorithm can greatly cut down the times of Kepler iterations and coordinate transformations, and effectively mitigate the computational burden of continuous prediction of time‑frequency synchronization parameters on terminals. The trade‑off between computational complexity and accuracy can be flexibly adjusted by tuning the interpolation interval. Requiring no modification to network‑side ephemeris broadcast signaling, the scheme can be realized purely at the terminal software layer and is applicable to various LEO satellite communication terminals with limited computing resources.

Abstract：To address the uplink margin bottleneck of direct-to-cell LEO satellite communications, an S-band 29 dBm high-power FDD handheld terminal is designed. The link budget sets the constraints of PA output ≥32 dBm, isolation ≥63 dB and NF ≤4 dB. An RF front-end built around a PA, a high-isolation SAW duplexer and a zenith 1T2R antenna is proposed, together with an IMD2 isolation model, two-stage Doppler compensation, PRACH segment detection, and thermal and SAR designs. Without DPD, the measured ACLR at 35 dBm is better than -40 dBc; drain efficiency is 34.3%~35.0% under fixed bias and the 40% power-budget target is to be pursued via bias and circuit-topology optimization, while around 60 dB isolation is measured over a 40 MHz bandwidth against the ≥63 dB design target. A detection probability of 0.98 is reached at 16 dB, and the measured 29.1 dBm conducted power, -96.38 dBm sensitivity and 79 ℃ junction temperature together verify the feasibility of the proposed design.

Abstract：Faced with large scale terrestrial cellular network outages induced by disasters, massive conventional user terminals will rapidly access low earth orbit satellite networks, resulting in limited satellite beam resources, severe co-channel interference, and low utilization of terrestrial licensed spectrum. Targeting 6G satellite-terrestrial cooperative non-terrestrial network (NTN) systems, this paper investigates cross domain radio resource management technologies for emergency communication scenarios. A system model of satellite service takeover under terrestrial network failure is constructed. On this basis, a hierarchical priority-based resource management strategy is proposed to jointly optimize power allocation, beam scheduling, and time-frequency resource configuration. Furthermore, a terrestrial network silence-aware dynamic spectrum reuse mechanism is developed, which enables the reuse of idle terrestrial licensed spectrum while guaranteeing the communication quality of residual terrestrial cells. Simulation results verify that the proposed scheme can significantly enhance the throughput of emergency critical services. This work provides effective theoretical support and technical solutions for 6G satellite-terrestrial emergency communications.

Abstract：To address the common nonlinearity and non-stationarity of time series data, as well as the issues of traditional prediction models being insufficient in capturing temporal dependencies and having low efficiency in adaptive parameter optimization, this paper proposes a time series prediction model based on an artificial fish swarm algorithm (AFSA)-optimized attention mechanism. This method preprocesses the original data using a rolling window strategy to preserve the intrinsic temporal correlations of the sequence. It uses an attention mechanism to adaptively learn the importance weights of inputs at different time points. And it introduces the AFSA to globally optimize key model parameters, improving the model's generalization ability and convergence performance. Experimental results on short-term electricity load data indicate that the proposed method outperforms comparative models in prediction accuracy and convergence speed, effectively reducing prediction errors and demonstrating stronger adaptability and predictive capability for non-stationary time series data.

Abstract：For the virtual staining task that translates unpaired H&E images into Ki-67 immunohistochemical images, an improved CycleGAN framework guided by the downstream task is proposed. By introducing a shared encoder and an auxiliary classification branch into the target-domain discriminator, the framework imposes semantic constraints on the generation process and improves the preservation of critical pathological features. In the context of postoperative early recurrence prediction for hepatocellular carcinoma, a complete pipeline that includes whole slide image preprocessing, virtual staining, and classification-based evaluation is established. The results show that, while the proposed method achieves generation quality comparable to that of the baseline model, it yields better semantic consistency and stronger downstream classification performance.

Abstract：The FlexRay bus features high transmission rates, high safety and stability, and excellent determinism, making it well-suited for automotive control systems. In order to reduce the workload of the CPU and quickly transfer data, a FlexRay bus interface with a dedicated DMA function is designed. The basic principles of the FlexRay bus, the overall structure of the FlexRay module, and the design and implementation of the dedicated DMA function are introduced. The simulation verification of the interface design shows that the FlexRay bus interface and its dedicated DMA functions are realized and successfully applied to a 32-bit microcontroller.

Abstract：Based on a dual-core system's microprocessor architecture, this paper proposes a low-power design scheme for the selected flash memory. The design achieves low-power operation in both normal working mode and sleep mode of the flash memory through power mode control of the flash controller, write/erase ownership control, and clock gating design. Silicon verification results demonstrate that the total chip current is 449.2 mA when the flash is executing read requests, and the total chip current drops to 415.7 mA when the flash enters sleep mode with the clock gated, representing a 7.46% reduction in total chip current, effectively reducing the power consumption overhead of the flash in the system.

Abstract：Aiming at the problems of high CPU load and insufficient bus bandwidth utilization due to large-scale data migration in SoC systems, a DMA controller for low-power platforms is designed based on AHB bus to improve data transmission efficiency and reduce CPU intervention. The design adopts a modular structure that includes register configuration, transmission control, FIFO buffering, and cross-clock domain synchronization modules, and uses linked list descriptors to realize automatic continuous transmission of multiple data blocks. In order to optimize the reliability in the asynchronous clock environment, a dual-trigger synchronization and handshake mechanism are introduced to ensure cross-domain stability of data. The functional correctness and performance of the design were verified through simulation and typical SoC data handling tests. The results show that the controller can operate stably at 200 MHz and has an area of about 10 700 μm², meeting the system's requirements for low power consumption and efficient data transmission.

Abstract：Enhanced PWM (ePWM) supports high-resolution dynamic adjustment of duty cycle and is widely used in fields such as motor control and photovoltaic inverters. This paper designs an ePWM circuit that achieves pulse-width modulation with a resolution of approximately 150 picoseconds (ps) based on Micro-Edge Positioning (MEP) logic. Additionally, the circuit incorporates a built-in self-test and diagnosis mode, which enables dynamic and real-time measurement of the optimal operating conditions of the MEP logic during operation. Having been successfully applied in the development of multiple chip models, this circuit can realize precise control and regulation of various devices, thereby enhancing the stability and reliability of the system.

Abstract：In precision machining processes, the reliability of the measurement system is a core factor in ensuring product quality. This study systematically evaluates the measurement data of a wall thickness micrometer used in a company's machining process based on the Gauge Repeatability and Reproducibility (GR&R) method from Measurement System Analysis (MSA), employing the widely adopted analysis of variance (ANOVA) method. The research aims to quantitatively assess the measurement capability of inspectors and verify the stability of the measurement process. Through calculations, key indicators such as Equipment Variation (EV) and Appraiser Variation (AV) demonstrated excellent performance. The results show that the measurement system's %GR&R is 8.31%, and the Number of Distinct Categories (NDC) is as high as 17, both significantly surpassing industry acceptance standards. The analysis indicates the measurement system is stable and reliable, capable of accurately distinguishing part variations, with inspectors exhibiting high operational consistency and fully meeting capability requirements. This study provides scientific quantitative validation of both inspector competence and the measurement system for this machining process, offering practical reference for maintaining high-quality standards.

Abstract：With the rapid development of e-commerce and social networking platforms, core business of the enterprise and other sensitive information has increased significantly, raising growing concerns about privacy leakage. To address the need for automatic identification and secure processing of sensitive information in unstructured text, this study investigates the application of large language models (LLMs) for detecting and sanitizing enterprise information. Using user texts from platforms such as Amazon, patient.info, and Facebook, a framework based on LLMs for sensitive information identification and desensitization is constructed. Through prompt engineering, the model identifies and evaluates the sensitivity of disclosed information and rewrites the original content under semantic-preservation constraints, thereby minimizing sensitive information disclosure while maintaining semantic consistency. ChatGPT is employed as the experimental model, and empirical results show that the proposed method can effectively identify sensitive health information in user-generated texts and generate sanitized versions with high semantic fidelity, providing a feasible approach for privacy protection and information security governance in unstructured text.

Abstract：The wireless communication environment is complex in Internet of Things(IoT) terminals, requiring low power consumption and support for ultra-long-distance communication. IoT application specific integrated circuit(IoT ASIC) is gradually becoming a typical solution for IoT terminals. IoT ASIC commonly uses fixed thresholds for detection during synchronization acquisition. However, the detection probability tends to fluctuate significantly under low signal-to-noise(SNR) conditions, leading to unstable communication. To solve the problem, this paper proposes an adaptive threshold detection algorithm based on peak-to-average ratio(PAR) tracking. By constructing a unique synchronization frame based on the Zadoff-Chu(ZC) sequence, the algorithm utilizes the peak-to-average ratio of the correction peaks for peak detection, while continuously tracking the relative positions of these peaks to achieve adaptive threshold adjustment and improved synchronization stability. Theoretical analysis and simulation results show that the adaptive threshold detection algorithm offers lower implementation complexity in ASIC applications, and exhibits better capture performance under low SNR conditions compared to fixed thresholds.

Abstract：To enhance the security protection capability of power monitoring systems in source-grid-load-storage interaction scenarios, a dynamic security architecture based on isolation vectors is adopted, designing terminal security component Agent and collaborative blocking mechanism. A unified management platform is constructed to achieve centralized management of isolation devices, establishing a closed-loop control system of "real-time collection-health assessment-policy verification-precise deployment". Test results show that the isolation vector platform reduces policy deployment time to 25 seconds, improving efficiency by 96% compared to traditional CLI configuration, the security component Agent achieves an average risk detection time of 3.2 seconds with local blocking latency under 2 seconds, and the end-to-network collaborative blocking completes within 9 seconds, showing 99% improvement over manual processing. This architecture achieves cross-security-zone collaborative protection, providing an effective security isolation solution for new power systems.

Abstract：In order to improve the command and flight control communications capabilities for long-range strikes, research was conducted on the architecture and networking technology of satellite-missile interconnect wireless communications system. A wireless communications architecture applicable to both VHF/UHF bands and satellite communication bands was designed. Rapid link establishment and networking could be fulfilled with basic communications system. With on-demand frequency switching to L/C/Ku bands, and access to phased array antennas, an enhanced communications system could be made. Then, a hierarchical wide-area network structure was designed, consisting of three layers: main station layer, base station layer, and terminal station layer. Finally, the networking technology and key indices were analyzed and calculated. The applicable scenarios of CSMA self-organized network and autonomous time-based SOTDMA network were disussed. The bandwidth, protected time slots, transmit power, space link attenuation, user capacity, and algorithm complexity were analyzed. Based on engineering verification, subsequent development ideas were proposed.

Abstract：This paper presents a 0.41-THz fully integrated amplifier-frequency multiplier chain implemented in 65-nm CMOS technology. The proposed signal source employs a two-stage cascaded frequency multiplier architecture driven by quadrature signals with two-way power combining. Direct coupling between the two multiplier stages eliminates the need for a 200-GHz balun, thereby reducing high-frequency insertion loss. In addition, the first-stage frequency multiplier integrates both frequency multiplication and power combining, providing sufficient drive power for the second-stage multiplier without relying on inefficient 200-GHz amplifiers. Furthermore, harmonic impedance optimization is achieved by controlling the impedance at the center tap of the transformer, which enhances the conversion gain while avoiding the additional loss introduced by the input matching network required in conventional harmonic impedance control techniques. During measurement, when driven by a 103.75 GHz input signal with an input power of 5 dBm, the chip achieves an EIRP of 9.7 dBm and a radiated power of -7.8 dBm at 415 GHz. The chip consumes 354 mW of DC power.

Abstract：To address the high integration, miniaturization, and lightweight requirements of phased array Transmit/Receive (T/R) subarrays in military equipment, this paper focuses on the research of Quad Flat No-lead (QFN) plastic-encapsulated T/R module technology. This approach aims to solve issues associated with traditional metal-packaged microwave modules, such as large form factors, numerous connectors, structural parts, printed circuit boards, assembly processes, and high costs. By conducting electromagnetic simulation design for key packaging parameters, the study addresses the poor high-frequency performance of existing plastic encapsulated products, achieving a chip-level integration of the Ku-band T/R module without connectors or enclosures. The overall dimensions of the 4-channel Ku-band T/R module are 12 mm × 6.6 mm × 0.75 mm, with a weight of 0.22 g. The measured electrical performance meets application requirements, providing a low-cost, high-performance, miniaturized, and thin technical solution for next-generation phased array radar systems.

Abstract：To further enhance the testing capabilities of the passive intermodulation (PIM) testing system and ensure the successful completion of key tasks in the field of communication satellites, this study aims to effectively utilize the characteristics of silicon carbide (SiC) absorbing materials, such as their high- and low-temperature resistance, high-power endurance, and low PIM performance, and convert these properties into experimental equipment suitable for ground verification of aerospace equipment. This paper proposes a novel pyramid absorber configuration specifically designed for PIM testing. It elaborates on the absorption mechanism of silicon carbide pyramid absorbers and provides optimization principles and configuration parameters for existing silicon carbide pyramid absorbers. Based on this foundation, the study presents a manufacturing scheme for a high- and low-temperature PIM test absorbing chamber using the optimized silicon carbide pyramid absorbers. Additionally, the paper provides the experimental results for the validation of the absorbing chamber's capabilities, demonstrating its temperature endurance in PIM testing across a range of -70 ℃ to +150 ℃.

Abstract：To fulfill the functional testing requirements for signal readout chips of Cadmium Zinc Telluride (CZT) detectors, a test system for CZT detector readout chips has been developed with the Cyclone IV series Field-Programmable Gate Array (FPGA) serving as the control core, encompassing hardware circuits, FPGA control logic, and an upper-computer interface module. The results show that the system can successfully configure the 192-bit register functionality of the chip via the upper-computer interface. The measured nonlinearity error of the chip is 1.8%, and all four analog signal gain functions operate correctly, confirming the proper functionality of the designed chip testing system. The chip testing system proposed in this paper also provides a valuable reference for other detector-specific signal processing integrated circuits.

Abstract：As an important component of the transmission terminal of wireless communication devices, the RF power amplifier circuit is highly unstable in output power due to differences in temperature, environment, and application scenarios in special applications. This paper designs an RF power amplifier circuit based on the ALC loop, aiming to provide a power control with high accuracy and stability. The paper introduces in detail the overall design scheme, working principle, and circuit structure of the RF power amplifier circuit, and proposes specific design methods and solutions for key circuits and technologies. Engineering practice has proved that the designed RF power amplifier circuit has good power flatness, high stability, and strong controllability, and has been successfully applied to various complex wireless communication electronic equipment.

Abstract：A long-life primary power switching circuit based on fully semiconductor devices is proposed for the satellite-borne atmospheric synchronous calibration instrument. The design employs an optocoupler for command isolation and level conversion, and utilizes a metal-oxide-semiconductor field-effect transistor (MOSFET) to achieve both inrush current suppression and power switching, along with a self-locking mechanism upon startup. A circuit model is established to analyze key performances including switching response, inrush current suppression, and noise immunity. A prototype is fabricated and tested under simulated space environmental conditions. Results demonstrate that the circuit operates reliably across a wide temperature range, with fast switching response, effective inrush suppression, and strong anti-interference capability, meeting the requirements for long-term, high-reliability, and frequent switching operations in orbit.

Abstract：In the high-speed communication scenarios driven by artificial intelligence and cloud computing, 100G Ethernet faces severe reliability challenges due to the deterioration of channel bit error rate. Based on the IEEE 802.3bj standard, this paper proposes an autonomous and controllable Reed-Solomon forward error correction (RS-FEC) circuit and designs a hierarchical multi-mode architecture to support active mode and transcode bypass mode. It integrates the dual-mode codec schemes of KR4 (RS(528,514)) and KP4 (RS(544,514)). The sender implements format conversion from 64B/66B to 256B/257B, Galois domain RS encoding and symbol distribution. The receiving end completes multi-channel reordering, RS decoding and reverse transcoding, and optimizes resource occupation and timing performance through the Vivado tool. A verification platform is built based on UVM, supporting bidirectional data flow detection and error injection, with a functional coverage rate of 100%. Experiments show that the circuit can correct 7/15 symbol errors respectively in the KR4/KP4 mode, and both the resource and delay indicators meet the requirements of high-speed Ethernet.

Abstract：Aiming at the demand of high-reliability and independently controllable controller devices for the commutation control of Brushless Direct Current (BLDC) motors, this paper designs a six-step commutation control system for BLDC motors based on a domestic dual-core RISC-V architecture Microcontroller Unit (MCU) (HKSR5102). Centered on the domestic MCU, the system is equipped with a three-phase full-bridge power drive circuit, multi-type rotor position detection circuits and signal sampling circuits. By adopting the six-step trapezoidal wave commutation strategy, it realizes forward/reverse rotation, speed regulation and stable operation control of the motor. Test results show that the system features accurate commutation logic, precise PWM timing and regular phase voltage waveforms. It can operate stably in the full frequency band without distortion, phase loss or phase jump issues.

Abstract：The high resolution radar profile (HRRP) contains rich target structural information and is one of the popular target features for radar target detection and recognition. This paper proposes a new method for retrieving the elevation information of large ship targets in high sea conditions based on HRRP. The ship’s feature parts distributed at different heights exhibit different swing amplitudes during its six-degree-of-freedom oscillatory motion, which is the inherent characteristic that manifests as inter-range cell shifts in the HRRP. The maximum range cell span of each feature part during oscillation is estimated by multi-scatterer clustering across consecutive frames. Combining with sea condition information and the underlying geometric relationships between the feature parts, the ship's elevation can be retrieved. Simulation results demonstrate that the root mean square error (RMSE) of the proposed elevation retrieval algorithm is 1.95 m under sea state level 5, indicating that the algorithm exhibits excellent elevation retrieval performance under high sea conditions.

Abstract：Maximum detection range is the core index of radar combat effectiveness and early warning capability. Its calculation accuracy directly affects the deployment scheme of air defense system and the direction of radar equipment research and development. Traditional radar maximum detection range calculation usually adopts fixed average radar cross section value, neglecting the influence of attitude change of rocket and other targets on radar scattering cross section during flight process, resulting in large deviation of calculation results. A method for calculating the maximum detection range considering the dynamic change of attitude is proposed. Based on the coupling relationship between omnidirectional radar cross section modeling, trajectory solving, signal-to-noise ratio and detection probability, the method can accurately predict the actual maximum detection range of rockets with different flight attitudes through multi-step iteration and variable step size search. Example verification shows that this method improves the accuracy of maximum detection range of rocket, and provides reliable basis for performance evaluation of radar system and optimal deployment of air defense system.

Abstract：In view of the complexity and manual participation in information extraction, making it difficult to effectively utilize guidance information for Flight Deck Aviation Support Job(FDASJ), an information extraction method is proposed. This method can automatically and efficiently complete the extraction of information from normative texts involved in FDASJ guidance documents. Based on pre-trained language models（PLMs）for general domains provided by existing NLP platforms, this method achieves automatic extraction of FDASJ guidance information by optimizing lexical analysis results and sentences pattern similarity measure, through predefined extraction strategies. The information extraction tool software developed using this method can accurately extract entity and relationship information contained in normative texts, thereby constructing a knowledge graph. This method does not require extensive corpus annotation or long training periods, offers strong interpretability and scalability, can adapt to new requirements, and has reference value for other fields. In the future, leveraging the advantages of large language models（LLMs） in semantic matching and reading comprehension tasks, the tool's sentence segmentation and grammatical completion functions will be optimized to expand the variety of texts the tool can extract.

Abstract：The development of modern high-performance processors is making remarkable progress on a daily basis, while the technical challenges and problems resided in CPU architectures or microarchitectures faced by chip designers are also getting severer than ever. For example, the cost of main memory access is raising dramatically, and the latency for address translation is overwhelming, which would inevitably affect the overall performance of program executions for high-performance processors. Among others, hardware prefetching is an effective method to improve the ratio of data cache hit, resulting in a much narrowed and tolerable memory access latency. In this paper, an introduction on the pattern-based data prefetching and execution-based data prefetching is given firstly, a brief analysis on the temporal, spatial, and pointer-detection prefetching is provided, a thorough discussion is dedicated to the methods of delta prefetching and footprint prefetching, and the comparison of design details between a few representative spatial data prefetchers is summarized. Moreover, this paper proposes a joint hardware prefetching design of data cache and page tables, whose key idea is to fully exploit the spatial memory correlations of page tables, and implement the data prefetching based on the page-table prefetching, for the purpose of further improving the performance of existing spatial data prefetching methods.