Abstract：With the deep development of integrated circuit technology to the nanoscale, network-on-chip (NoC) has received extensive attention as a key technology to solve the communication bottleneck in multi-core systems. Based on the latest research results, this paper discusses several aspects of key issues affecting the development of NoC, including typical technologies and recent progress in topology, routing algorithms, switching mechanisms, and quality of service, etc. The study shows that some current emerging technologies significantly enhance the performance of NoC, such as lowering the communication latency, improving throughput, optimizing the power control, and increasing the resource utilization rate. Nevertheless, they still face many challenges such as high integration difficulty and difficult traffic management. Finally, this paper summarizes the existing problems of NoC technology and discusses the future development trend.

Abstract：With the development of semiconductor advanced processes nodes, the scale and complexity of integrated circuit designs is increasing, which brings great challenges to circuit simulation and verification. Accelerating circuit simulation with SpectreX-GPU has greatly improved the verification efficiency of large-scale, high-precision and complex circuit with advanced process nodes and has broken through the bottleneck of simulation and verification. SpectreX-GPU is a new engine in Cadence Spectre family with true spice accuracy. SpectreX-GPU expands simulator’s computation capability on CPU-GPU heterogeneous computing, combining the huge parallel computation capabilities of GPU with the complex operations of CPU. That makes SpectreX-GPU get high performance and balance between two capabilities and keep high accuracy same as SpectreX simulation engine. This paper introduces using SpectreX-GPU to accelerate simulation and verification in different types of cases on GPU device. It helps designers shrink simulation time, improve verification efficiency and coverage without accuracy loss.

Abstract：Design migration between different process nodes is a hot topic of concern for every IC designer. To help IC designers solve this problem, Cadence collaborates with major foundries worldwide to develop new technologies that efficiently migrate circuit diagrams to new nodes and use updated analysis tools to ensure optimal results. Virtuoso Schematic Migration (VSM), an advanced circuit migration platform based on Schematic XL in Virtuoso Studio IC23.1, helps engineers quickly migrate their designs between different processes to significantly reduce the circuit design cycle and improve R&D efficiency. This tool not only supports collaborative migration between multiple libraries but also supports hierarchical migration at the circuit top level.

Abstract：With the evolution of high-performance computing chip design toward advanced process nodes, the exponential growth in chip integration has led transistor density to surpass hundreds of millions of gates per square millimeter. This has resulted in the continuous narrowing of metal line widths in Power Distribution Networks (PDNs), a nonlinear rise in via resistance, and synchronized switching behavior of high-density logic units under GHz-level clock frequencies, significantly exacerbating IR Drop risks. Leveraging the Cadence Voltus Insight AI feature, this paper proposes a comprehensive voltage drop optimization solution for the physical implementation of high-performance CPU cores. By integrating AI-driven IR-Aware placement, reinforce_pg, and Watch Box repair technologies, the solution dynamically predicts current distribution hotspots in PDNs, optimizes the placement of high-power logic units, and enables proactive prevention and efficient mitigation of IR hotspots. Experimental results demonstrate that, under identical conditions, the approach not only saves time and improves efficiency but also elevates the IR Drop repair rate from 66% to 96%, while avoiding degradation in timing performance and Design Rule Check (DRC).

Abstract：This paper proposes an optimization and simplification scheme for spec files (auto_spec flow) based on the Cadence Innovus clock tree synthesis and optimization engine COD. This scheme eliminates redundant content in the automatically generated specs by the tool and reorders the commands according to their types, making it easier for users to read and manage the spec files. Additionally, the auto_spec flow addresses common issues in clock tree synthesis, such as the impact of DFT clocks on functional clocks and the influence of generated clocks on the main clock. It includes scripts for handling DFT clocks and automatic recognition and processing of generated clocks. Experimental results show that the auto_spec flow can effectively improve work efficiency, reduce clock latency, enhance clock quality, and is of great significance for the improvement of chip PPA.

Abstract：To reduce the modeling time for extracting power S-parameters using PowerSI, improve the accuracy of power supply simulations for internal functional modules in chips, and further identify power supply noise in sensitive regions, a distributed modeling method based on package power supply and a determination approach for practical noise measurement points were introduced. Applying this method to study power supply simulations of functional modules within a system processor chip, it was discovered that in time-domain power supply noise simulations, functionally similar power modules under the same data flow exhibit similarity in generated noise characteristics. Building on this observation, a distributed power supply model was established to group functionally analogous power modules. The grouped package power S-parameter models and die-level RC models were then integrated into time-domain power supply noise simulations. Based on simulation results, the locations of sensitive noise measurement points at package bumps were determined. Comparative simulations and measurements demonstrated that under alignment of main frequency components in the noise frequency domain, the time-domain simulation-measurement error remains below 6%, validating the effectiveness of the proposed distributed simulation methodology.

Abstract：With the continuous development of the XR field, the demand for fully functional and highly complex XR chip systems is increasing. The growing scale and complexity of chips pose significant challenges to verification convergence. How to achieve convergence of key verification metrics before tape-out has become a critical challenge for verification engineers and project managers. To address this, an EMU full-scenario AVIP rapid iteration verification solution is proposed. The EMU platform adopts Cadence Palladium Z2, where AVIP adapts to the Palladium Z2 EMU environment based on Cadence VIP. It interfaces with protocols such as PCIe, MIPI, USB, and UART, while meeting requirements for simulation acceleration, data comparison and others. By applying this solution to XR chip systems, verification convergence efficiency is effectively improved, providing robust support for tape-out decisions

Abstract：With the increasing demand for chip computing power in the fields of AI and high-performance computing, the chiplet solution is attracting more and more attention in the industry. However, the expansion of complexity and scale in multi-Die systems leads to issues such as high server resource consumption during simulation and extended verification delivery cycles. To solve these problems, this paper analyzes the traditional three-step method and socket verification method, and focuses on the Cadence distributed simulation solution. Based on an actual chiplet project, this paper breaks down system-level simulation tasks into multiple sub-Dies for parallel execution, and explores distributed simulation measures to improve efficiency from multiple aspects, such as server memory, cross-server communication delay, precise synchronization time adjustment, signal connection start time, and signal connection quantity. This achieves ultra-large-scale chiplet system-level RTL simulation and improves regression efficiency.

Abstract：With the development of deep learning, video-based water level detection has become a research hotspot in recent years. To improve the accuracy of water level measurements in urban rivers, reservoirs, and other water bodies, this paper proposes a 5G intelligent water level gauge detection system. The system primarily involves the hardware design centered around the Starshine SSC338G and a water level detection method based on an improved YOLOv8n. The method first identifies the orientation of the water gauge, then performs grayscale and binarization processing on the gauge images. Finally, YOLOv8n is used to recognize characters and scale information on the gauge, allowing for the calculation and analysis of water level data. By incorporating the attention mechanism EMA and replacing the loss function with Focal-EIoU, the improved model achieves a 21% reduction in the number of model parameters, a 17% reduction in model size, and a 21% reduction in floating-point operations.Comparative experiments with human-eye observations demonstrate that the model's accuracy meets the requirements, thus fulfilling the design goals for an intelligent water level gauge system.

Abstract：According to the operation scenario of control system for nuclear power plant, the problems existed during loading engineering configuration data for a kind of DCS platform based on variable address are analyzed. A non-interference incremental downloading technology is studied here, including the optimization and improvement of engineering configuration software, controller, data service and human-machine interface. Through design verification and practical engineering application, it is shown that the incremental download scheme can effectively recover idle address bits, determine the corresponding relationship between variable address and variable identification, prevent the dislocation of field data and the misaction of actuator. Finally it can improve the operation efficiency of DCS and the safety of nuclear power plant.

Abstract：In order to solve the problem that Doppler radar echo signal to noise ratio is low in complex electromagnetic environment, a VSS-LMS adaptive noise cancellation method based on improved tongue⁃like curve is proposed. By adding feedback to the original step iteration formula and filter weight coefficient iteration, the overall anti-interference performance of the algorithm is improved, and the compensation is added to the step iteration to speed up the initial iteration of the algorithm. The simulation results show that the proposed algorithm can effectively restore the target signal in the noisy signal with the minimum mean square error of 0.004 5, the maximum correlation coefficient of 0.95 and the maximum output SNR of 10.60 dB under the SNR of 0 to -10 dB. The measured results show that the proposed method has outstanding performance in the noise reduction of radar echo signal, and the mean square error is at least 0.005 5, which is suitable and effective in the actual noise reduction of electromagnetic signal.

Abstract：Most current recommendation methods based on knowledge graphs focus on the encoding mechanism of knowledge associations, often neglecting the potential key collaborative signals in user-item interactions. This leads to the learned embedding vectors of existing models being unable to effectively represent the latent semantics of users and items in the vector space. To address this issue, this paper proposes a multi-head attention network that integrates knowledge graphs and collaborative filtering - the collaborative knowledge-aware multi-head attention network (CKAN-MH). This network introduces a multi-head attention mechanism on the basis of the traditional CKAN model to adaptively focus on different subsets of features and perform differential weighting of tail entities by dynamically adjusting attention weights. After introducing the multi-head attention mechanism, the model can more comprehensively capture the complex relationships and patterns hidden in the data, thereby significantly improving the performance of the recommendation system. Additionally, we conducted experimental evaluations on three real datasets using the CKAN-MH model. The experimental results show that the CKAN-MH model outperforms several current mainstream advanced baseline models in terms of performance, verifying the effectiveness and superiority of this model.

Abstract：The Cyclic Redundancy Check Aided Successive Cancellation List (CA-SCL) decoding algorithm, as the list size increases, requires substantial space storage resources, leading to its inability to be applied under resource-constrained conditions. To address this issue, a partitioned polar code design method based on embedded CRC has been proposed. This method leverages parallel processing within partitions and sequential processing between partitions to significantly reduce storage resource consumption. By capitalizing on the superior error detection capabilities of the designed embedded CRC multiple checks and the innovative sequential list decoding algorithm between partitions, the code performance is further enhanced. Simulation results demonstrate that the proposed algorithm achieves superior decoding performance with notably lower storage resource consumption compared to the CA-SCL decoding algorithm.

Abstract：The conventional methods of digital image edge detection include Canny algorithm, Sobel algorithm, Prewitt algorithm, etc. On the basis of studying the calculation principle of the conventional methods of image edge detection, a digital image edge detection algorithm is proposed, which includes the preliminary extreme edge matrix calculation of the image, the suppression calculation of the Otsu threshold and the extension calculation of the edge. The feasibility of the proposed algorithm is verified by comparing the image edges extracted by the proposed algorithm with the image edges extracted by the conventional algorithms. The proosed algorithm and the corrventional methods are used to detect the edge of the engine nozzle burning flame image. The results show that the Sobel algorithm and the Prewitt algorithm the edge of a small amount of flame, the Canny algorithm provides the large outline of the flame, and the proposed algorithm provides a large amount of flame detail edge information. Because the edge of the combustion flame is an important feature of combustion, the proposed algorithm is more suitable for the depth analysis of the digital image edge of the nozzle burning flame, and provides a new method for the nozzle burning flame analysis.

Abstract：Traditional image encryption algorithms face limitations in the protection of highly sensitive data, transmission efficiency, and diverse applications. This study proposes a multi-image encryption algorithm based on a hyper-chaotic system and computational holography. The algorithm generates high randomness and complexity in chaotic sequences by combining the improved Logistic chaos and six-dimensional Cellular Neural Network (CNN) chaos, enhancing the security of the encryption process. The encryption effect and attack resistance are further strengthened by integrating random phase encoding with Fourier transform-based computational holography. To improve transmission efficiency, compressed sensing is applied to compress and encrypt multiple images, reducing data transmission volume and key consumption. Simulation results show that the proposed algorithm improves image security, significantly enhances transmission efficiency, reduces transmission time, and maintains low image distortion across different encryption strengths. Experimental results confirm that the algorithm effectively resists common attacks, offering strong security and high transmission efficiency. It is suitable for the protection of sensitive data in fields such as healthcare, finance, and other high-security applications.

Abstract：Cyberspace mapping platforms are capable of achieving efficient detection, integrated analysis, and mapping of various network assets, thereby providing a data foundation for network asset management, exposure analysis, and security protection. However, with the continuous increase in the types and quantities of detection targets, existing mapping platforms are unable to meet the needs for flexible detection of multiple sources and targets sin terms of rapid organization of detection networks and efficient utilization of detection resources. To address this, this paper studies and proposes a detection network organization and management model for heterogeneous multi-environment scenarios. This model effectively enhances the platform's organization and management capabilities through node management, task management, resource management methods, and API design. The model's usability and flexibility have been validated through testing.

Abstract：An 8~12 GHz 60 W high power amplifier is proposed in this paper based on the 0.25 μm GaN HEMT. The output power synthesis network adds parallel LC to the ground branchesbased on the Bus-bar synthesis network to optimize the balance of each pipe core, which makes the overall structure of the chip is compact and easy to match. The input second harmonic impedance matching technology is adopted to improve the high frequency band without affecting the output power. The output stage matching structure adopts two-stage series inductance and capacitance matching, which matches the output stage impedance to the target impedance and achieves low matching loss. Under the test conditions of 100 μs pulse width and 10% duty cycle, the saturation output power of the amplifier is greater than 48 dBm in the 8~12 GHz frequency band, the efficiency is greater than 35%, the power gain is 23 dB, and the chip size is 3.97 mm×5 mm.

Abstract：In this article, a K-band frequency conversion module is designed, which includes up and down conversion channels to achieve frequency conversion between K-band RF signals and intermediate frequency signals. By conducting full-link cascading simulation analysis and calculation, the frequency planning of the link was optimized, and the in-band spurious interference was reasonably avoided. Through three-dimensional electromagnetic field simulation, the transmission interconnection structure of the link was optimized, and the inter-stage matching characteristics were improved. The test results show that the component has the characteristics of high spurious suppression system and small in-band gain fluctuation. The spurious suppression is better than 60 dBc, in-band fluctuation is better than±1 dB, and mirror frequency suppression is better than 50 dBc. All other indicators meet the design requirements. This design method also provides beneficial exploration for the design of frequency conversion modules.

Abstract：According to the requirements of W-band radio frequency (RF) front-ends, a couple of W-band four-channel up-conversion transmitter and down-conversion receiver modules based on ceramic packaging technology are designed . Both modules employ a single-conversion architecture. Through mixing, amplification, and filtering, the input intermediate frequency (IF) signal at the bandwidth of 78~80 GHz transforms into the output signal at the bandwidth of 92~94 GHz, and then the output signal transmits into the antenna port. The down-conversion receiver module processes W-band signals through low-noise amplification, mixing, and filtering, and then converts the signal to the bandwidth of 78~80 GHz for further processing at the back-end. The local oscillator (LO) signal for the front-end operates in the X-band, providing power division and signal amplification functions to supply LO signals for multiple channels. In order to realize the high performances，high stability and low cost of the RF modules, a filtering and transmission structure based on the load on package (LOP) technology is studied. The measured results of prototype show that the W-band up-conversion transmitter module achieves an output power over 12 dBm, the power gain is greater than 6 dB at the frequency of 92~94 GHz. The W-band down-conversion receiver module exhibits a noise factor less than 9 dB and a gain greater than 10 dB within the operating bandwidth.

Abstract：With the rapid development of space technology, the reliability of chips in the irradiation environment becomes more and more prominent. In this paper, based on the RISC-V architecture high-performance processor C501, the triple modular redundancy and error detection and correction are used to harden the circuit level and system level respectively. At the same time, the strategy of memory access request forcing miss is adopted to correct the data block of check error, so as to improve the error-correcting ability of the cache system. The simulation outcomes indicate that the radiation harden processor is capable of rectifying cache data errors caused by irradiation. At the same time, the maximum working frequency has witnessed a decrement of 8.8%, the area increased by 64.9%, while the performance level has been maintained.

Abstract：Based on the analysis of the traditional Phase Sensitive Demodulator (PSD), this paper presents a PSD used in the stabilization loop of gyro platform. This circuit adopts unique circuit topology, solved the problem of traditional circuit of large volume, complex circuit etc. The output zero voltage is reduced by an order of magnitude through reasonable designed of parameters and thin-film technology. It greatly improves the zero position characteristics of circuit, and is of great significance to improve the performance of the whole machine.

Abstract：To address the challenges in power supply encountered during the testing of complex electronic equipment, and to enhance the automation level of the testing process, an integrated multichannel digital programmable power supply is designed. An integrated multi-channel digital programmable power supply is an innovative power device that utilizes computer control technology to achieve precise control over multiple power outputs, boasting notable advantages such as high efficiency and energy saving. The article, first of all, provides an overview of the fundamental principles and structure of an integrated multi-output digital programmable power supply. It then delves deeply into the design process and core technical innovations. Finally, it discusses the potential value and prospects for application in the field of automated manufacturing production. Practical engineering applications demonstrate that the designed integrated multi-channel digital programmable power supply possesses several advantageous features including ease of operation, high reliability, superior performance, strong versatility, and good scalability. These features enable it to effectively address practical issues and can be widely promoted and applied.

Abstract：L-band phased array antennas are widely used in maritime satellite communication due to their advantages of being less affected by environmental factors such as rain attenuation, mature transceiver technology, and low manufacturing costs. With the continuous development of airborne satellite communication antennas towards miniaturization and low profile, this poses higher challenges for the design improvement of phased array antennas. On the premise of meeting the performance requirements of ARINC-781-8, compared to rectangular grid arrangement, triangular grid arrangement can effectively suppress grid lobes and improve phased array scanning performance due to its compact layout. At the same time, this layout structure requires fewer antenna units, making it easier to achieve miniaturization and low-cost design of antenna terminals. This article takes a certain L-band 2×6 triangular grid layout maritime satellite communication phased array antenna as the design object, models the key mathematical model of the triangular grid layout structure, introduces the development method of this type of antenna, designs a beam scanning control algorithm suitable for the antenna terminal, and implements it on FPGA. The physical prototype of the antenna was subjected to static experiments in an outdoor environment with the communication terminal. The physical prototype can achieve stable communication with the maritime satellite system and has excellent communication quality.

Abstract：The multi-channel DC power supplies for TR modules in phased array radar antennas require strict power-on sequencing to prevent latch-up effects and avoid high-voltage false triggering when logic circuits are not initialized. Addressing the engineering requirements for power-on sequence control of three commonly used independent non-common-ground power supplies (+28 V, +5 V, -5 V) in TR modules, this paper proposes a hierarchical control circuit based on the three-terminal voltage regulator TL431 and optocoupler isolation. The circuit achieves electrical isolation between non-common-ground power supplies through optocouplers and precisely controls the power-on timing sequence of each voltage by integrating TL431-based threshold protection circuitry. Featuring low-cost implementation and easy scalability, this solution provides an effective approach to managing power-on sequences in multi-channel independent power supply systems. It offers reliable design references for industrial equipment requiring multi-voltage power supply configurations.