Abstract：The integration of wireless network and TSN(Time Sensitive Networking) is one of the concerns of industry at present. The traditional gateway based on application layer software has some disadvantages, such as high CPU utilization, long processing delay, poor performance and so on. Therefore, a WiFi TSN low delay conversion architecture is proposed to realize the integration of WiFi network and TSN network. The architecture is implemented in Verilog language, which ensures the predictable delay between communication channels through hardware, and can complete protocol conversion and protocol data forwarding in a very short time. Vivado EDA tool is used to complete the circuit design, and sufficient simulation tests are carried out to evaluate the end-to-end delay performance of the circuit.

Abstract：This paper introduces a kind of physical layer fieldbus chip architecture and its implementation in accordance with IEC 1158 standard. The chip is designed with Manchester codec circuit, Cyclic Redundancy Check(CRC) verification circuit, carrier detection circuit, polarity correction circuit and other functional circuits. The high-speed interface circuit of Advanced eXtended Interface(AXI) is used as the data transmission bus with external processor. The task has completed the RTL code writing of this chip, and carried out a comprehensive time series simulation. The chip function test is carried out on ZYNQ-7015 as hardware platform. The test results show that the chip meets the design requirements.

Abstract：In view of the coexistence of various fieldbus protocols at present，three principles of bus protocol conversion are proposed based on the analysis of CAN bus protocol,MODBUS bus protocol and HART bus protocol，including bus address conversion principle,bus protocol frame conversion principle and bus error notification conversion. And on the basis of this protocol conversion principle，the hardware architecture of fieldbus protocol conversion is proposed to improve the real-time performance of protocol conversion.

Abstract：In order to adapt to the current factory equipment, aiming at the huge amount of equipment and data transmission, this paper designs a new HART modulation and demodulation core interface, which uses AXI4 bus interface to replace the traditional UART interface to accelerate the communication speed between HART modulation and demodulation chip and CPU. Compared to the traditional URAT interface, the AXI4 bus interface can transmit 32 bits of 8 bytes in parallel, and the data transfer speed can reach the NS level. Through the interconnection of AXI4 bus module and CPU, the structure function configuration and data interaction are realized. The high-speed communication interface design of HART modulation and demodulation chip was verified based on FPGA platform. The results show that the architecture can effectively identify HART communication protocol, the data interaction between CPU and HART chip reaches NS level, and the correct rate of modulation and demodulation reaches 100%, which meets the requirements of HART communication protocol.

Abstract：With the development of information technology, the coverage of industrial Ethernet is increasing, and the interconnection of industrial networks becomes the basis for the transformation of modern factories to intelligent and digital. Firstly, the paper expounds the development policy of industrial Internet in China, the current situation of the industrial network market and the types of industrial Ethernet protocols to analyze the current obstacles to the interconnection of industrial networks. Secondly, the paper explores new methods for new technologies to promote the interconnection of industrial Ethernet networks. Finally, the paper puts forward constructive suggestions according to the status of industrial Ethernet and industrial Internet to promote the application of industrial Ethernet and the development of industrial Internet.