Abstract：With the explosive growth of data generated by the widespread use of cloud computing, Ethernet, and the Internet of Things (IoT), the demand for wired input/output (I/O) bandwidth in large data center networks has surged rapidly. The development of high-speed Ethernet aligns with the rapid growth of network traffic. However, as the data transmission rate of Ethernet increases, the challenges related to signal integrity in serial links are further amplified. This paper focuses on the challenges faced by Ethernet equalization technologies under high-speed transmission, analyzing various equalization techniques in depth. It explores the working principles and characteristics of different equalizers and discusses their applicability in high-speed transmission environments. The paper provides a reference for the future development and optimization of high-speed Ethernet equalizers, aiming to better meet the growing demand for higher transmission efficiency and lower bit error rates in communications.

Abstract：In this paper, a system verification architecture for time-sensitive network (TSN) switch chip, which is based on UVM, automatic comparison and coverage-driven verification thinking, is designed. This architecture adopts the method of classifying and pipelining packets, combined with traffic detection, time slot detection and packets automatic comparison scheme, successfully satisfies the implementation of the TSN system verification method, finally ensures the system verification completion. Chip test results meet commercial requirements, once again demonstrates verification architecture completeness.

Abstract：This study proposes a crossbar matrix transmission design based on adaptive optimization, employing the Advanced High-performance Bus (AHB) protocol. It introduces innovative mechanisms for adaptive burst transmission adjustment and adaptive priority adjustment. By dynamically adjusting burst transmission length and priority allocation, efficient data flow management is achieved, improving bandwidth utilization and transmission efficiency. Front-end simulation and back-end layout routing were conducted to validate the design. Simulations confirm the method’s superiority under different load conditions, optimizing bus resource allocation, increasing transmission speed, and reducing overall power consumption.

Abstract：Dynamic Random Access Memory (DRAM) is widely used in modern large-scale computers and ultra high speed communication systems due to its high storage density and cost-effectiveness. This article mainly introduces the development history, key technologies, domestic and international research progress, and future development directions of dynamic DRAM. Firstly, the classification, basic unit structure, and working principle of DRAM are introduced. Secondly, the key performance indicators of DDR SDRAM and the development of dedicated DRAM are introduced in detail. Then, innovative DRAM architectures and technologies that improve DRAM access speed, capacity, and density are introduced, as well as capacitor free storage cell structures, 3D stacked DRAM technology, and Rowhammer security issues and defense mechanisms. Finally, the future development direction of DRAM technology is discussed, and the importance of in-depth research and innovation on existing DRAM technology is emphasized to meet the growing demand for high-speed, low-power, and high reliability storage.

Abstract：As one of the key technologies to realize the vehicle intelligence, the automotive data transmission technology with high speed, high reliability, and low latency, is getting more and more attention. At the same time, the demand for breaking the monopoly of proprietary protocols and enhancing interconnectivity between devices is growing increasingly, driving the development of public standards on automotive data transmission to be a hot topic for many domestic and international standard organizations. This paper firstly introduces the features of the automotive data transmission link. Then, the progress of the mainstream standards is briefly summarized, with a special focus on the high-speed automotive data transmission physical layer interface chips. We conduct a comprehensive comparison and analysis of the main performance indicators and physical layer technologies for these standards.

Abstract：LDPC code is a widely-used high-performance error correction code. In recent years, LDPC decoding based on deep learning and neural networks becomes a research hotspot. Based on the (512,256) LDPC code of the CCSDS standard, this paper firstly studies the traditional decoding algorithms of SP, MS, NMS, and OMS, laying a foundation for the construction of neural networks. Then a data-driven (DD) decoding method is studied which adopts the information with its encoded, modulated and noise-added LDPC code as the training data within a Multi-layer Perceptron (MLP) neural network. In order to solve the problem of high bit error rate (BER) in data-driven method, the Neural Normalized Min-sum (NNMS) decoding in which the NMS algorithm is mapped to the neural network structure is proposed, achieving more excellent BER performance than that of NMS. The BER declines by 85.19% when channel SNR equals to 3.5 dB. Finally, improved training methods to enhance the SNR generalization ability of the NNMS network is studied.

Abstract：With the rapid upgrades of products such as AI PCs, Wi-Fi routers, and GPON, high-speed wired network is an essential part of network infrastructure, Ethernet PHY chips have to provide higher transmission rates to better meet the growing bandwidth demands in the era of big data. 10G Ethernet technology is bound to become the key evolution direction for the next generation of Ethernet. The development of 10G Ethernet PHY chips need to overcome a series of technical challenges, including high-speed signal integrity and low-power design. This paper focuses on the key issues of signal processing in 10G Ethernet PHY chips, firstly introducing the background of relevant international standards for 10G Ethernet, then discussing the network requirements for 10G Ethernet, and next describing the key technologies for signal processing at the physical layer of 10G Ethernet. Finally, the paper makes a summary and outlooks the further development of high-speed Ethernet.