Abstract： In order to meet the diversified requirements of airborne display, this paper proposes a video conversion and overlay technology based on FPGA. The technology takes FPGA as the core, and is equipped with peripheral circuits such as decoding circuit and signal conversion circuit, which can realize the conversion of XGA and PAL analog video signals to RGB digital video signals, and overlay display with digital image signals. It has strong versatility and flexibility. The experimental results show that the video conversion and overlay technology can meet the requirements of stable, reliable and highly integrated picture display of airborne displays, and has high application value.

Abstract：With the rapid development of technologies such as intelligent driving and robots, conventional 2D detection algorithms cannot meet the requirements of environmental perception in these scenarios, and 3D target detection is required to obtain accurate environmental information. However, the current mainstream 3D target detection models based on multi-source data fusion rely on high-computing and high-power platforms, and are difficult to implement on low-performance embedded platforms. In response to these problems, a method for implementing multi-source fusion 3D target detection on a low-power FPGA platform is proposed. By fusing the LiDAR point cloud and camera image data, the lack of point cloud feature information is compensated to achieve higher accuracy and detection stability. At the same time, combined with the characteristics of the FPGA platform, the fused features are screened and processed, and the model is compressed in combination with a quantization strategy. After experiments, the fusion method significantly improves the accuracy of small objects, and the quantized model runs successfully on the end-side FPGA platform with an average 3D accuracy loss of less than 3%.

Abstract：With the increasing application of visible light imaging and infrared imaging in various scenarios, integrated design concept is adopted to develop the compact dual-mode imaging and processing platform. The platform employs RK3588 and ZYNQ as main processor and coprocessor, enabling parallel real-time processing of 1080P visible light images and 1 280×1 024 resolution uncooled infrared images. Under the control of software algorithms, it can achieve real-time target tracking and recognition. Through field tests and high-low temperature tests of physical prototypes, the platform demonstrates stable and reliable performance with a compact structure, meeting the requirements of multiple application scenarios such as UMV, USV or UAV .

Abstract：Aiming at the problems such as the low generalization ability of traditional methods in road defect detection, which are vulnerable to environmental interference, and the high power consumption and low speed when deploying deep learning models on computing platforms, an acceleration and deployment strategy for the semantic segmentation model based on a low-power FPGA (Field-Programmable Gate Array) platform is proposed. Firstly, a multi-source dataset containing road cracks and potholes is constructed, and data augmentation techniques are used to balance the sample distribution. Secondly, channel pruning is carried out separately for the feature extraction network and the upsampling network of the UNet model. Combined with the quantization technique, the model weights are compressed from FP32 (32-bit floating-point) to INT8 (8-bit integer), further reducing the computational load. Finally, the Vitis AI toolchain is utilized to complete the model quantization and compilation, and the model is deployed to the FPGA platform to fully exert its parallel computing capability. The experimental results show that, on the premise of ensuring that the loss of the mean intersection over union (MIoU) is less than 5%, the inference speed of the optimized model reaches 17 ms. The number of model parameters and the computational load are significantly reduced, and the power consumption is remarkably decreased. This method achieves efficient and low-power road defect detection at the edge side, providing a feasible solution for the automated maintenance evaluation of asphalt roads.

Abstract：For coping with transmission and display problem caused by the huge amount of seamless spectrum data in real-time spectrum analyzer, this article designed a FIFO-based frame detector of real-time spectrum analyzer in FPGA. It combines multiple frames of spectrum data into one frame for transmission and refresh while retaining signal characteristics. By simulation and actual testing，results show that the detector has four types of detection: peak value, negative value, mean value and real-time sample value. It also can cut off the spectrum data outside the analysis bandwidth while detecting. Compared with the traditional RAM-based frame detector, the detector does not need to control RAM read and write addresses, is easy to implement, occupies less logic resources, and has been applied in real-time spectrum analyzers.

Abstract：When applying a cardiac scan, the image reconstruction only needs the expose data that sampled in the cardiac diastolic phase, and other periods sampled data are discarded. Therefore, the forward-looking scan pattern can be used in order to reduce the radiation dose. Due to the different cross sections of the scanning plane, the dose of modulation(DOM) can be used to reduce the radiation dose further. According to the attenuation difference of the cross section of the scanned object at different angles, the DOM adjusts the mA value based on the angles in real time, so the DOM can improve the xray efficiency and reduce the radiation dose. By combining the characteristics of the two, a forward-looking automatic tube current modulation control system for cardiac scanning is designed, which realizes the effect of reducing cardiac scanning radiation and getting good image quality.

Abstract：As a new type of communication system，FH communication has strong characteristics of anti-interception,anti-search,ant-interference and anti-antagonism. FH communication system is adopted in the tactical information distribution system,ground and shipborne and airborne FH radio stations and identification friend or Foe systems of the United states and NATO countries,which has high confidentiality and anti-interference performance.In view of the characteristics of high speed FH signal with wide frequency band,many frequency points and fast frequency hopping speed,this paper proposes to use two pieces of ADRV9009 RF agility chip to transform the high speed FH signal into zero IF signal,and then send it to PFGA through polyphase filtering digital channelization to complete the signal receiving and processing.The design not only simplifies the whole signal front-end wideband reception process,reduces the volume of the front-end analog channel receiving equipment,and reduces the power consumption of the system,but also greatly increases the flexibility of the syetem,and improves the detection and identification probability of high-speed frequency hopping signal in the end.

Abstract：Concerning the security threats such as firmware tampering and malicious code implanting in the startup process of system on a programmable chip(SoPC), a secure startup model is proposed. The model takes boot ROM as the trust root, and the public key algorithm and symmetric cipher algorithm are used to sign the firmware in each phase of the startup process. The digital signature value of each firmware image is verified in turn after SoPC is powered on, so as to establish a complete trust chain. In the implementation stage, the model is designed and verified by using Intel field programmable gate array(FPGA) development platform, and two secure boot modes are realized. The results show that the model can be applied to chip development to meet the requirement of secure startup.