Abstract：For real-time problem, this paper presents a speaker′s voice recognition system solution that makes the FPGA as the hardware platform. The system consists of four parts: signal acquisition, endpoint detection, feature extraction and identification. The experiment results show that the time-consuming is 15.932 ms on the 4 codebooks and 50 MHz-clock system, the identification rate is 93.3% on the 12 codebooks system. This kind of design improves the system′s recognition speed, which is an effective program to solve the real-time problem.

Abstract：Using distributive lattice theory， a wire-speed multicast switching fabric based on a multi-path self-routing fabric structure is constructed which is implemented on the platform of an Altera StratixIV FPGA chip. Also, it is investigated how the structure is used in large scale multicast switching fabric，and the signaling system and control mechanism are designed to support the process of self-routing and wire-speed fan-out copy of multicast packets.

Abstract：This paper proposes a new means which is implemented on FPGA. It filters the salt and pepper noise and has two steps to detect the noise. And this paper builds a platform of this arithmetic on the DE2 platform.

Abstract：In this paper, a new VLSI architecture which is to do two-dimensional transformation is designed to deal with problems of a large number of process data storage and critical path delay existing in the realization process of two-dimensional wavelet transformation. The FPGA implementation has been achieved on an Altera Cyclone II EP2C35F672C6. Under pure calculation logic, tow-dimensional wavelet transform clock frequency can reach 157.78 MHz.

Abstract： This paper proposes a method of realizing wavelet transform algorithm, which is based on FPGA. Using high and low pass decomposition filter to realize wavelet transform algorithm,DB5 is taken as basis function to establish analysis model of five disturbance signal of transient power quality for the simulation and do simulated power signal test based on FPGA hardware platform. Contrasting signal source and test results with the singular point start-stop and duration, the results show that the method is feasibility and accuracy.

Abstract：To tackle the bottleneck of data-caching and the transmission speed in the high-speed data acquisition system, a new high-speed data transmit-save system is designed in this paper. Via utilizing the Stratix IV GX series FPGA, as well as the built-in DDR2 IP core and high-speed send-receive IP core of Quarturs II, the local port of PCI9056, DDR2 controller, fiber channel protocol and transformation and sending of high-speed serial data are realized. Based on it, a new high-speed data-caching and transmission system is implemented.

Abstract：Digital down converter DDC is the core technology in software radio receiver system. After converting down, speeding down and processed by low-pass filter, it can change the IF signal into baseband signal which is suitable for processing signal. This paper introduces a simply and flexible method to realize each module of DDC in FPGA，and get the real-time operation of the system with the SignalTap II logic analyzer.

Abstract： A kind of UHF RFID active tag design method based on EPC Gen2 is presented in this paper. Tag’s hardware circuit is made of three parts: reflex circuit, receiving circuit and baseband control circuit. By theoretically analyzing, a low bit-error-rate design proposal is presented for the reflex circuit. Two-channel quadrature demodulation program is adopted to design the receiving circuit. And an FPGA chip(EP1C3T100C6) is adopted to design the baseband control circuit. Using a reader to test the tag, testing results of oscilloscope, frequency spectrograph and upper computer show that tag works well.

Abstract：According to the differences of fingerprint quality，an enhanced pretreatment process with multi-index integration fingerprint image quality evaluation is introduced in this paper. The fingerprint can be classified by humidity and quality，and the low quality fingerprint which can be restore gets enhovnce pretrertment based on wavelet transform. The whole algorithm is verified by Matlab，and the process is implemented in a SOPC platform based on DE2. The results of experiments show that the process can judge the availability of fingerprint effectively and improve the quality of poor fingerprint significantly.

Abstract：This paper proposes a new Chen-Mobius communication system and briefly describes the FPGA design，functional simulation and hardware implementation of the new Chen-Mobius communication system based on the DE2 board.

Abstract：Aiming at the problem of poor precision and low speed in the application of ordinary ultrasonic ranging, we put forward a full hardware realization of FPGA-based ultrasonic ranging system. The system realizes ultrasonic echo envelope fitting by least squares method of quadratic curve fitting algorithm, which can calculate the distance through the process of echo signal. The digital circuit is described by Verilog HDL, and the system is implemented on Altera′s EP2C70F896C6. The measurement error is less than 1 mm in range of 4 meters. System′s measure precision is high and operation speed is fast. System can be extended on the field of ultrasonic flaw detection and ultrasonic imaging, etc.

Abstract：Image rotation is a necessity for 2-D barcode identification. This paper presents a novel VLSI structure for image rotation which can calculate the tilt angle of 2-D barcode image and rotate image to the horizontal way. The circuit to calculate the tilt angel of 2-D barcode is simple and effective and can be implemented with low hardware complexity. Image rotation algorithm takes use of improved CORDIC algorithm and Bi-linear interpolation and is implemented by high-speed pipelined architecture. The proposed architecture is implemented on the Altera Stratix IV FPGA. The whole design is validated in Altera's DE2 workbench. Experimental results show that the proposed architecture can rotate 2-D barcode images with arbitrary tilt angles to the horizontal way at 90.9MHz. Moreover, it can keep image details clear thus improving 2-D barcode identification rate.

Abstract：To meet the high precision of the doppler velocity measuring sonar, the broad band transmitting signal and phased-array are used, also with the high speed, parallel, real-time characteristic of processing data by FPGAs, the digital system of the Doppler velocity measuring sonar is designed and implemented on the core of Altera’s StratixII EP2S60F484I4 FPGA , the sampling control, band-pass filtering, beam forming, correlation operation and other signal processing algorithms have been realized . Meanwhile, the test results show that the broad band signal can meet the high precision of sonar system better.

Abstract：Parallel structures of BCH encoder/decoder are implemented, for application of NAND Flash. The design is composed of LFSR circuit module, syndrome solving module, key equation solving module and Chien search module. They are described in register-transfer level and realized on FPGA platform. The design is verified on an embedded SoPC platform. Under the control of Nios CPU, BCH algorithm can be efficiently tested. This embedded test system has the virtue of configurable test environment, high test-vector coverage and intelligent test process.

Abstract：A novel implementation, based on the memory polynomial and multi look-up tables of adaptive digital predistorterdevice(DPD) is presented in this paper and realized in a Dual-core Nios II processor. With the parallel recursive least square(RLS) algorithm realized in two Nios II cpus, the efficiency of computation of parameters extraction process in DPD is greatly improved. Moreover, the results of experiment suggest that the implementation proposed by this paper can well compensate the nonlinearity of the power amplifier.