Abstract：Based on the standard 0.18 μm process, a digital decimation filter applied to the Sigma-Delta analog-to-digital converter is designed, which can change the decimation rate and adapt to different signal bandwidths. The filter adopts multi-stage decimation and consists of a cascaded integrator comb filter, a compensation filter and a half-band filter. The realized digital filter can be changed in the decimation rate of 64，128，256 and 512. Compensation filters and half-band filters of different bandwidths are also designed. The filter area is 0.6 mm×0.6 mm. Under 1.98 V working voltage, the total maximum power consumption is about 2 mW, and the highest signal-to-noise ratio reaches 110.5 dB. When the passband frequency of the compensation filter and the half-band filter is selected according to the bandwidth from the highest to the lowest, it can save 61% and 53% of the power consumption respectively; When the filter power consumption being the smallest 69.63 μW, the bandwidth that can be processed is 390.6 Hz, and the signal-to-noise ratio is 107.8 dB.

Abstract：For the status quo of lack of high-performance platforms that support the access, management and operation of upper-layer applications such as dynamic planning and operation optimization of digital twins in regional multi-energy systems, this paper takes into account the requirements of digital twin applications for communication efficiency and data security, with the help of CloudPSS cloud simulation platform, the software and hardware of a secure, flexible, and scalable digital twin application platform including the basic layer, application layer, and business layer are designed. Taking Guizhou Hongfeng Lake regional multi-energy system as the pilot area, it introduced the construction process of the regional multi-energy system digital twin application platform including modeling and simulation, data communication and application integration functions. The built regional multi-energy system digital twin application platform serves as an ideal tool for realizing digital twins from concept to application, its architecture design plan and specific construction experience can provide theoretical and practical references for the wide implementation of digital twin technology.

Abstract：High penetration of renewable energy in power grid challenges power system operation and stability evaluation, due to the fast dynamic behaviors of power electronic devices. The accurate broadband impedance measurement is one of the critical aspects of power system stability analysis. The impedance measurement method of injecting harmonics to the actual power system may bring the risk of instability. The hardware-in-the-loop simulation technology can achieve accurate broadband impedance measurement with lower cost and risk. The computing accuracy and simulation scale of real-time simulators depend on the computing power of the target computer. As the demands of large-scale power system increase, a single real-time simulation system may not meet the requirements. Co-simulation between multiple real-time simulators is an effective way to increase the scale of the simulation. This paper proposed an online impedance analysis co-simulation framework based on the CloudPSS-RT and RT-Lab platform and verified the accuracy and effectiveness of the co-simulation by constructing a PV and DFIG power generation system.

Abstract：Redis is an unstructured database based on memory storage. It is known for high I/O(Input/Output) performance and high response speed. It plays an important role in data buffering, message queues, key-value storage and other scenarios. Among the many clients it supports, the C/C++ client Hiredis is particularly widely used. This article did an in-depth analysis of the Hiredis library and found that its pipeline function has high overhead, improper instruction storage, and memory confusion problems. Based on this, this article designs and implements a C/C++-oriented high-performance and high-availability Redis client on a 32-core X86 architecture processor and a 64 GB memory Linux server. It improves the performance of processing a large number of instructions and solves the problem of memory confusion in complex scenarios through memory pre-allocation and memory isolation. After testing, the new client has improved instruction execution efficiency by 3～7 times, while also ensuring memory safety and accuracy in complex scenarios.

Abstract：The new generation Global/Regional Assimilation and PreEdiction System(GRAPES) is a homegrown numerical weather prediction software developed by China Meteorological Administration(CMA). As the requirements for model resolution and prediction timeliness increase, the Input/Output(I/O) performance of GRAPES becomes a critical performance bottleneck. This paper performs a deep analysis of I/O behavior for the GRAPES regional model，and proposes, designs and implements a high-performance I/O framework. This framework achieves a flexible and configurable output method through binary encoding and multiple I/O channels. At the same time, asynchronous I/O is included by non-blocking communication, which hides the I/O and communication overhead. The framework has been tested on the Sugon Pai supercomputer, and the results show that the framework can not only improve I/O performance by up to over ten times but also reduce the performance uncertainty caused by performance jitter.

Abstract：CWRF(Climate-Weather Research and Forecasting model) is a component of the regional climate prediction system built in the National Climate Center, and consumes the largest proportion of time. High performance computing is a key technology used to improve the compactional performance of CWRF. Carrying out the configuration and optimization of the CWRF model based on the domestic Sunway many-core system, improving the simulation efficiency are of great significance for the speedup, as well as the development capability and sustainable development of the model. This paper completed the configuration and performance evaluation of CWRF based on the SW26010 many-core architecture. Memory access optimization, Cache hit rate optimization, many-core acceleration models are introduced to speedup CWRF relating to the dynamic-core process, physical process and I/O process. The results show that the average speed of the dynamic process is 2 times and the highest speed is 6.4 times, the average speed of the physical process is 1.7 times and the highest speed is 5.4 times, the I/O process speeds up 1.2 times, the overall program speeds up to 1.4 times, and the calculation error is reasonable.

Abstract：The Community Earth System Model(CESM) is a numerical model to quantitatively describe the change of climate system model, which is one of the most important research objects in the field of high-performance computing because of its huge volume of scientific computing. The load imbalance between each meteorological sub module and component of CESM makes its computing performance unsatisfactory. It is not realistic to retrieve the optimal layout manually by enumerating parameters because the diversity of available process layout schemes will lead to a huge amount of retrieval. In order to solve this problem, this paper proposed and implemented a retrieval strategy based on the matrix-nesting idea of load balancing optimization scheme to help the process layout and intervenes in the screening work based on the parallel requirements of the original model. Finally, the experiment proved that the optimal layout obtained by this search strategy search had a performance improvement of 47.3% compared with the default layout and achieved an acceleration ratio of 1.419 on 5 nodes.

Abstract：Traditional sorting methods are mainly implemented in software serial mode, including bubble sorting, selective sorting and so on. These algorithms often use sequential comparison, and the operation time complexity is relatively high. In recent years, some sorting algorithms with a high degree of parallelism have been proposed, but due to the hardware characteristics of the CPU, the parallelism of these algorithms cannot be used well. And FPGA has the characteristics of good flexibility, parallelism and integration, so the advantages of these parallel algorithms can be better utilized on FPGA, thereby greatly improving the real-time performance of data sorting. Based on this, the paper designs a CPU-FPGA heterogeneous system, transplants some sorting algorithms to FPGA, and performs functional verification and theoretical performance evaluation. The results show that the system has a good acceleration effect for sorting algorithms with high parallelism, but consumes huge logic resources, and is suitable for algorithm acceleration scenarios with high real-time requirements.

Abstract：The traditional CORDIC(Coordinate Rotation Computer) algorithm has many iterations, slow convergence speed, and large resource consumption for high-precision arctangent. An improved high-precision CORDIC algorithm is proposed. This method uses the traditional CORDIC algorithm to obtain the sine information after several iterations, and uses the sine value to compensate the error of iteration results，which effectively improves the calculation accuracy. Experimental data shows that the 32 bit improved CORDIC algorithm ensures that the absolute error is less than 5×10-9, the resource consumption of the lookup table is reduced by 64.8%, the resource consumption of the flip-flop is reduced by 35.3%, and the output delay is reduced by 53.3%. In molecular dynamics application scenarios, flip-flop resource consumption can be reduced by 63.2%, and output delay can be reduced by 60%. The improved CORDIC algorithm is superior to the traditional CORDIC algorithm in terms of resource consumption and output delay, and is suitable for high-precision computing applications.

Abstract：Digital-analog hybrid simulation is essential for understanding the real power grid and supporting power grid security. Complex power network topology and hard real-time simulation put forward high requirements for computing performance. At present, digital-analog hybrid simulation mainly uses parallel computing technology to improve computing performance. With the development of processor and cluster technology, heterogeneous cluster systems have gradually become the primary construction method of high-performance computing systems. For the multi-level system architecture, the existing power grid division methods can not fully use the cluster computing power. Dealing with the high latency of cross-layer communication and the unequal number of available processor cores on each computing node due to heterogeneous acceleration equipment is the main challenge of the partitioning and mapping algorithm. Aiming at the electromagnetic transient simulation system ADPSS developed by China Electric Power Research Institute, this paper designs a two-stage integrated optimization algorithm of power grid division and process mapping, which achieves a better load balance and minimizing communication, and further reduces the calculation time of the electromagnetic transient simulation. The algorithm is based on the min-cut partition and effectively solves the optimal mapping of sub-networks of unequal sizes on heterogeneous cluster systems. The simulation test was realized on the real power grid in Northwest and East China, compared with the ADPSS default partition and mapping algorithm, the proposed algorithm achieves an average communication performance improvement of 40% and 50% and an average overall computing performance improvement of 10% and 12%.

Abstract：In order to solve the problem of insufficient human-computer interaction ability of ball training partner robots, a new human-computer interaction mode based on Raspberry Pi and YOLOv5 algorithm was proposed, which enabled the robot to realize six different actions: forward, backward, left, right, throwing the ball, and kicking the ball. After calibrating and training the data sets collected in three different environments(indoor, outdoor sunny day and outdoor cloudy day), the recognition accuracy of the six poses in the test set under three different environments is 96.33% indoor，95% outdoor sunny day，and 94.3% outdoor cloudy day, respectively. Compared with other algorithms based on feature matching and small target detection using gestures, the robot has higher detection speed and accuracy, which makes the robot more intelligent.

Abstract：Aiming at the efficient classification and handling of domestic waste, this article designed a photoelectric smart car system with the edge embedded AI device Jetson Nano as the controller. The system is designed with YOLOv5 as the target detection algorithm and Pytorch1.8.1 as the deep learning framework. The system makes the smart car start from the designated location, search for garbage in the designated area through its own photoelectric sensor, identify and classify the garbage, and use the six-axis robotic arm to sort the garbage and send it to the designated stacking place. 300 iterations of training were performed on the collected 5 048 pictures and 5 types of garbage. The experimental test results show that the average accuracy reaches 91.8%, the accuracy rate reaches 94.5%, and the recall rate reaches 89.03%.

Abstract：In recent years, how to recognize and analyze people′s facial expressions through artificial intelligence has become a research hotspot. Using artificial intelligence can quickly analyze people′s facial emotions, and further research is carried out on this basis. In deep learning, the traditional convolutional neural network can not extract facial expression features sufficiently, and the amount of computer parameters is large, which leads to low classification accuracy. Therefore, a facial expression recognition algorithm based on VGG16 neural network is proposed. Compared with the model experiments of InceptionV3, InceptionResNetV2 and ResNet50, the results show that the recognition accuracy of VGG16 neural network on FER2013PLUS test data set is 79%, which is higher than that of traditional convolution neural network.

Abstract：An active bidirectional mixer performing the up/down conversion is proposed at K-band with a 130 nm CMOS in this paper. The mixer performs the down conversion in the Rx mode and converts the radio frequency(RF) signal amplified by low noise amplifier(LNA) into the intermediate frequency(IF) signal, whereas carries out the up conversion in the Tx mode and shifts the baseband(BB) signal up to the RF signal for the power amplifier(PA). Post-simulation results shows that with 0 dBm local oscillator(LO) drives, the mixer achieves the conversion gain(CG), noise figure(NF), and output 1 dB compression point(OP1dB) of -1.1~ -0.4 dB, 12.9~13.3 dB from 23 to 25 GHz, and -8.2 dBm@24 GHz in up-conversion mode, respectively. In down-conversion mode, the mixer exhibits the CG, NF, and iutput 1 dB compression point(IP1dB) of 2.4~3.4 dB, 15.2~15.6 dB from 23 to 25 GHz, and -3.6 dBm@24 GHz, respectively. The chip area is 0.6 mm2, which consumes 12 mW from a supply of 1.5 V.

Abstract：With the growing demand of embedded system miniaturization and the performance of analog-to-digital/digital-to-analog converter(ADC/DAC), it is a big problem how to improve the reliability of ADC/DAC signal transmission, increase the function configurability and signal processing reconfigurability on the premise of reducing system volume and power consumption. Thus, this paper designs a system in package(SiP) prototype verification platform based on FPGA, used to verify the feasibility and reliability of this SiP architecture.

Abstract：The HDLC signal link is the high level data link control(HDLC) developed by the international organization for standar- dization(ISO). The article follows the HDLC standard data link layer specification, uses the hardware description language Verilog HDL to implement a parallel structure-based HDLC frame search and decapsulation circuit, and uses System Verilog technology to build a verification platform, and randomly generates HDLC data frames to verify the correctness of the design. Using Modelsim software to simulate waveforms, during the simulation process, for HDLC data frames with a payload area of 10 bytes, the decoder circuit requires 16 clock cycles to complete the work, taking into account processing speed and flexibility. Using QuartusII software synthesis, on Altera CycloneV devices, the circuit uses 8 adaptive logic modules ALM, 24 registers, and 35 pins.

Abstract：Aiming at the problem of the first frame loss and the mis-establishment of the link caused by the interference during the initial link establishment of LVDS transmission, this paper analyzes the link transmission mechanism and stability, and optimizes it from both hardware and software aspects. The software adopts the method of identifying the frame header and sending the training frame to improve the link building process. The hardware chooses a better performance electriciacl isolation chip and optimizes the differential terminal impedance to reduce the impact of interference on data transmission. Many tests have proved that the optimized link can achieve reliable transmission at a rate of 480 Mb/s. This optimized design has a good reference value for improving the transmission stability of the LVDS link and reducing errors.

Abstract：Brake-by-wire technology is one of the key technologies of pure electric smart cars. In order to improve the safety and stability of automobile braking, it is necessary to study the control logic of the anti-lock braking system of a pure electric smart car. Before the implementation of this program, a reasonable logic threshold is set for simulation experiments. In this paper, a vehicle dynamics model with 8 degrees of freedom is built based on Simulink to simulate the braking conditions in a curve, and the differential control of the vehicle is realized by controlling the yaw moment of the vehicle. Through simulation experiments, the rationality of the proposed anti-lock braking system control logic is verified, which has guiding significance for the subsequent research and development of brake-by-wire systems.

Abstract：This paper analyzes the IEEE 802.11e enhanced distributed control access protocol in detail, compares the difference between the distributed coordination function DCF and the enhanced distributed control access EDCA, and proposes a four-dimensional Markov chain model. The model unifies the saturated condition and the unsaturated condition. This model not only considers the freeze state of the backoff timer, the transmission conflict state and the maximum number of retransmissions, but also fully considers the internal conflicts and TXOP transmissions of different access priority streams. Compared with the two-dimensional Markov chain model, this model can accurately predict the throughput of access flows with different priorities in EDCA. At last，simulation software is used to verify the correctness of the model under saturation conditions.

Abstract：For the problem of identifying the same user across social networks, a recognition method that integrates user interests, writing style and profile attributes is proposed. By determining user relationships under these three different feature dimensions separately, and then synthesizing the results, the same user identification accuracy is improved. Among them, user interest is divided into static interest and dynamic interest, static interest is extracted from user background information by TextRank algorithm, while dynamic interest is mined from user published text content by using topic model to find out interest points that change over time. For user writing style, it is identified by One-Class SVM algorithm, and finally, the information entropy empowerment method is used to compare the similarity of user profile attributes. The experimental results show that the proposed algorithm has improved accuracy and recall rate compared with traditional machine learning algorithms.

Abstract：In view of the low precision and low efficiency of panel surface defect detection, this paper proposes an optimized defect detection algorithm based on Faster R-CNN. This method adds local adaptive cross-channel convolution without dimensionality reduction in the feature fusion layer to increase the feature mapping of channel crossing，and adds the CBAM attention network after the backbone feature extraction network to capture the long-term feature dependency of the feature map . It also analyzes the difference in the aspect ratio of the defect data set, sets the generation size of the aiming window, and combines the DIoU-NMS suggestion frame screening mechanism to improve the matching rate of the prior frame and the target frame. Experimental results show that the accuracy and recognition rate of the optimized network model have been greatly improved.

Abstract：With the rapid development of Internet of Things, cloud computing, big data, mobile Internet, artificial intelligence and other new technologies, the following security problems are more serious. More and more unknown attacks and vulnerabilities make the traditional network security defense methods difficult to adapt. The principle of network security defense system based on dynamic camouflage technology is to construct the false appearance of the uncertainty of the external characteristics of the system by dynamically changing the types, quantity and characteristics of loopholes, defects and backdoors, so as to achieve the purpose of concealing the real loopholes, defects and backdoors of the information system.

Abstract：Aiming at the existing target detection algorithms based on sparse representation, in the process of building the background dictionary with concentric double windows, the target pixels will interfere with the background dictionary. A sparse representation hyperspectral target detection algorithm based on background dictionary is proposed. The algorithm decomposes the hyperspectral image into low rank background and sparse target, and introduces the target dictionary as the prior information of sparse target, which can separate the target and background better and construct a pure background dictionary. Simulation results on four public hyperspectral image datasets show that the proposed algorithm has excellent detection performance.

Abstract：Business process management is an important enabling technology for organizations to build information systems. To ensure the correctness of micro processes, this paper proposes an approach to modeling and analyzing micro processes. Firstly, micro processes and micro processes composition under synchronous communication and asynchronous communication models are modeling based on Petri nets. Secondly, the soundness of composite micro processes is analyzed based on the Petri net analysis technology. Experimental results show that the proposed method can model microprocesses and detect the deadlocks caused by synchronous or asynchronous interaction errors of the composite micro processes.

Abstract：When the electromagnetic signal penetrates the medium, its signal intensity will be reduced due to the scattering of electromagnetic waves and other reasons, and even change the polarity of electromagnetic waves. In order to measure the influence of electric charge on electromagnetic wave attenuation, this paper designed an electromagnetic wave attenuation experiment with dielectric plate, and selected typical dielectric plates such as PP plate, PVC plate and PMMA plate to conduct an experimental study on electromagnetic wave signal attenuation. The results show that the attenuation of electromagnetic wave is enhanced when the dielectric plate is charged, and the attenuation is enhanced with the increase of electric quantity.

Abstract：A miniaturized ultra-wideband receiver module is designed for electronic reconnaissance system in this paper. The receiver module contains two down-converter receiving channels, two LO synthesizers and a self-checking circuit in limited area. The module is of superheterodyne with twice frequency conversion by millimeter wave local oscillator，and the miniaturized circuits based on a series of multi-function MMICs are designed. To reduce the thickness and lateral dimensions，the through holes between microwave circuits and control circuits are adopted for interconnection. To realize self-calibration function，self-calibration synthesizer generates a signal，and then the ADC collects the voltage of DLVA，finally the gain and the consistence of two receiving channel are optimized based on adjusting the digital attenuators. Through above steps, the receiver module is easily manufactured, thus batch production efficiency is improved.

Abstract：A vertical interconnection structure based on a stack of multi-layer silicon interposer boards is designed. The simulation results of the vertical interconnection structure of the two interlayer structure not considering and considering the SiO2 layer on the silicon surface were compared in the DC-60 GHz frequency band. The existence of the SiO2 layer has an impact on the radio frequency performance such as resonant frequency and impedance. The parameters of the latter vertical interconnection structure are optimized, its RF transmission performance is good, and the return loss S11 is less than -30 dB when the frequency is below 40 GHz, the overall S11 is less than -15 dB below 60 GHz, and the insertion loss S12 is greater than -0.32 dB below 50 GHz. This paper simulates and analyzes the influence of the thickness of SiO2 insulation layer on the silicon surface on the transmission performance of the radio frequency signal. The results show that appropriately increasing thickness of SiO2 insulation layer can help optimize the performance of the vertical interconnection structure.

Abstract：In response to the requirements of satellite L-band communication and forwarding systems, a novel type of satellite-borne L-band broadband high-gain circularly polarized microstrip antenna is designed. The microstrip antenna adopts a side-fed feeding method as a whole, adopts an H-shaped slot coupling feeding method to achieve a wide frequency band, and uses a Wilkinson phase shift power splitter to achieve the phase difference between the two signals to meet the circular polarization, and add the antenna back reflector and foam layer between the boards to increase gain and stabilize the structure. Through the analysis of electromagnetic simulation software, it can be obtained that the gain is 8.3 dBi at the center frequency point of 1.45 GHz, the axial ratio is 0.7 dB, the relative bandwidth is 23.5% when the gain is greater than 7.5 dBi and the return loss is less than -10 dB. The actual measurement results of the antenna processing are basically consistent with the simulation results, which have certain guiding significance for the design of the L-band wireless communication system.