Abstract：The development of LiDAR technology provides abundant 3D data for autonomous driving. However, LIDAR point cloud is actually incomplete 2.5D data due to signal loss caused by occlusion and some reflective materials, which poses a fundamental challenge to 3D perception. To solve this problem, this paper proposes a method for 3D completion of the original data. According to the symmetric shape and high repetition rate of most objects, the complete shape of the occluded part in the point cloud is estimated by learning the prior object shape. The method first identifies regions affected by occlusions and signal loss, and in these regions, predicts the occupancy probability of the shapes of objects contained in the regions. For the case of occlusion between objects, 3D completion is performed through the occupancy probability of the shape and the morphologies that share the same shape. The objects occluded by themselves are restored by mirroring themselves. Finally, it is learned through the point cloud target detection network. The results show that this method can effectively improve the mAP for generating point cloud 3D borders.

Abstract： In order to minimize the accuracy loss when compressing huge deep learning models and deploying them to devices with limited computing power and storage capacity, a knowledge distillation model compression method is investigated and an improved multi-teacher model knowledge distillation compression algorithm with filtering is proposed. Taking advantage of the integration of multi-teacher models, the better-performing teacher models are screened for student instruction using the predicted cross-entropy of each teacher model as the quantitative criterion for screening, and the student models are allowed to extract information starting from the feature layer of the teacher models, while the better-performing teacher models are allowed to have more say in the instruction. The experimental results of classification models such as VGG13 on the CIFAR100 dataset show that the multi-teacher model compression method in this paper has better performance in terms of accuracy compared with other compression algorithms with the same size of the final obtained student models.

Abstract： With the development of power user information collection system, richer user electricity consumption information is used for the identification of user electricity consumption information anomalies. In this paper, a false data injection based on the FDI attack is performed to construct a dataset of user electricity consumption information anomalies, and an improved stacking integrated classification algorithm based on recall is proposed. K-nearest neighbors algorithm (KNN), random forest model (RF), support vector machine (SVM) and gradient decision tree (GBDT) are used as the scheme of base classification model of the stacking structure. Logistic regression (LR) is used as a meta-classification model of the stacking structure. The output of the basic classification model is weighted based on the recall rate, which is used as the input data set of the meta-classification model. The proposed improved stacking classification algorithm based on recall is shown to be more efficient than the traditional stacking classification algorithm.

Abstract：As designs become more complex, constrained randomized verification methods have become the mainstream method for verification. Generally, the verification incentive should be as random as possible without violating the spec description condition, so that the space that the verification can cover is more sufficient. However, this brings great challenges to the convergence of functional coverage. To solve this problem, Cadence pioneered the machine learning function of the simulator - Xcelium Machine Learning, which uses machine learning technology to quickly converge the functional coverage and greatly improve the efficiency of verification simulation. This article mainly introduces the process of using Xcelium Machine Learning and gives a comparison before and after using machine learning in the same simulation verification environment. Finally, the application prospect of machine learning in simulation verification is prospected.

Abstract： As the chip manufacturing process is approaching the physical limits, multidie stacked 3DIC Chiplets design has become one of the best ways to continue Moore's Law. Integrity 3D-IC platform integrates design planning, physical implementation, and systematic analysis into one single management interface, providing a comprehensive solution for 3DIC design. In conventional die-by-die flow, after 3D structure is established，two or more dies are implemented phsically and independently. Besides, the tool supports concurrent multidie implementation flow with placement and routing simultaneously in two dies. This work uses Cadence Integrity 3D-IC to establish concurrent multidie implementation flow, including parallel two-die placement , 3D unit (Hybrid Bonding bump) position optimization, clock tree synthesis and routing. The results show the comprehensive performance of concurrent PnR flow is better than die-by-die flow.

Abstract：With the continuous improvement of the integration of high-performance computing chips and the advancement of technology, the width of metal wires is getting narrower and narrower, and the voltage drop (IR drop) will occur on the power network when the resistance on the chip power network increases and the high-density logic gate unit has a logic flip action at the same time, resulting in timing problems in the chip, and even the functional failure of the logic gate may occur. Based on the flash PG flow of the Cadence implementation tool Innovus, this paper completes the comprehensive implementation and rapid iteration of the PG network, and uses auto reinforce PG and trim PG to realize the trade-off between the voltage drop and timing of the high-performance CPU core from two aspects, and completes the whole process optimization of the PG network from floorplan to PR (Placement and Route) stage. The results show that under the premise of the same machine resources, flash PG flow can increase the speed of powerplan up to 10 times the original, especially in the design of the top level, which can effectively save the exploration time of PG mesh in the early stage of design. Auto reinforce PG and trim PG repair 66% of the dynamic IR drop violations by reinforcing the PG of the weak IR area and trimming the redundant PG respectively, and at the same time provide more winding resources for the design to achieve the purpose of not deteriorating the timing and DRC (Design Rule Check).

Abstract： With the continuous development of semiconductor technology, the scale of chip design is increasing. That makes much more complicated parasitic need to be considered in designs and also makes post-simulation cost much more loading. This article will discuss how to use Cadence's parasitic extraction tool Quantus for post-layout parasitic extraction, and use Quantus' Standalone Reduction(Qreduce) function to simplify the post-imitation netlist to reduce the size of the netlist and increase the speed of simulation. Cadence's Qreduce function is to perform equivalent operations on the RC network through mathematical operations to reduce the number of nodes, thereby reducing the size of the netlist, but at the same time ensuring that the accuracy will not cause a relatively large loss. This article will discuss the degree of post-simulation netlist reduction, the impact of simulation accuracy, simulation speed and memory consumption, and give key comparison indicators.

Abstract：With the development of silicon process size to the level of single nano, it has been more and more difficult to continue Moore's law. Advanced packaging solutions with heterogeneous integration, such as 2D Flip-Chip, 2.5D and 3D, will continue to meet market requirements for miniaturization, high performance and low cost, thus become the main direction of continuing Moore's Law. But it also presents new challenges, especially for system-level LVS checking. In this paper, Cadence Integrity 3D-IC tool was used to perform system-level LVS checking for different types of advanced packaging, which fully verified the effectiveness and practicability of the tool and ensured the reliability of heterogeneous integration packaging system solutions.

Abstract： This paper uses Cadence's SystemSI for DDR whole channel simulation, and the interposer fixture developed by EDADOC Technology for testing. After multiple verification simulation with testing data, the DDR simulation and testing method offered by this paper can achieve high accuracy. With the increasing demand for memory bandwidth, the limitations of DDR4, the current mainstream, are becoming increasingly obvious. This paper illustrates the specific technologies for improving the signal integrity of DDR5 through specific cases, and demonstrates the advantages of DDR5 in the process of memory upgrading through simulation comparison.

Abstract：With the advance of the chip process, the scale of digital chips has increased sharply, and the cost of testing has further increased. Advanced DFT technology has been used on large scale SoC chips, including scan path design, JTAG, ATPG (Automatic Test Pattern Generation) and more. However, for some small scale integrated circuits (analog front end chips for example), inserting test circuits, such as scan chains, will increase chip area and add additional power consumption. For this kind of chip, the test pattern generated from functional simulation cases can be used to detect the manufacturing defects and failures. Therefore, there should be some methodology to verify if the coverage has met the goal, especially for automotive chips.Cadence Verisium Manage Safety Client, relying on core engines of Xcelium Fault Simulator and the Jasper Functional Safety Verification App (FSV) can solve this problem. It provides a credible coverage for ATE (Automated Test Equipment) pattern.

Abstract：Aiming at the problems of low coupling efficiency and few mode of transmission into fiber of existing quasi-distributed liquid leakage monitoring fiber sensor, a short focal length Fresnel lens was designed for the sensor light source. Through the simulation analysis of Zemax software, the specific Fresnel lens is designed and manufactured, and the light source used in the fiber sensor can be better converged. By comparing the coupling power of the LED with or without the lens, the results show that the power of optical coupling into the fiber with the lens can be increased by 40% and the other sensing properties are not affected. The designed Fresnel lens can couple the light source efficiently and improve the resolution effectively when the length of the sensing band is the same.

Abstract： To obtain the two-dimensional velocity distribution at the shallow or cross-section of the water and expand the application range of ultrasonic measurement, a two-dimensional side-looking acoustic Doppler velocimeter was designed. A 5 MHz high-frequency ultrasonic wave was used for measurement, and a unique probe structure was designed to avoid interference to the measuring flow field. Based on the basic principle of the Doppler effect, the complex autocorrelation algorithm was used to estimate the frequency, and the radial velocity of ultrasonic transducer was calculated. The two-dimensional velocity was obtained through the transformation matrix. The experimental results show that the designed two-dimensional side-looking acoustic Doppler velocimeter can effectively measure the two-dimensional velocity of the sample with the standard deviation of 0.047 m/s and 0.009 m/s respectively, which has certain practical value.

Abstract：In order to solve the problem of low-temperature cold storage and cold start of vehicle-mounted proton exchange membrane fuel cell engine at -30°C, this paper proposes a measurement system for measuring the monolithic AC impedance of on-board fuel cell engine. The monolithic current and voltage signals are processed by a band-pass filter circuit, and the monolithic impedance is calculated by a fast Fourier transform. When collecting impedance, the monolithic voltage is collected through another control core, realizing simultaneous dual collection of monolithic voltage and impedance.In the system shutdown strategy, the monolithic impedance is used as the shutdown criterion, and after it reaches the threshold point of low temperature storage and cold start, the system stops purging and completes shutdown. The system can be stored at -30°C and cold started, and finally used in batch applications at the Beijing 2022 Olympic Winter Games.

Abstract： Traditional hybrid Angle-Of-Arrival (AOA)/Received Signal Strength Indicator (RSSI) localization methods require all of the anchor nodes to be equipped with the large scale of antenna arrays to achieve high accuracy of localization. To solve the problem of low localization accuracy under the resource constraint of anchor nodes, a hybrid AOA/RSSI cooperation localization method based on mesh networks was proposed. With only one central anchor node providing AOA angle information, the angle and distance information of real and virtual anchor nodes was integrated to estimate the preliminary localization by using the least square method. Then, the cooperative communication and ranging information between unknown nodes was added to the overall localization process, and the localization estimation problem was converted into an unconstrained non-linear optimization problem, higher weights were given to the short-range links, and the cooperative localization was solved by iterative solving. Simulation results show that the proposed algorithm effectively improves the localization accuracy under the resource constraint of anchor nodes.

Abstract： In order to meet the current demands for clear, long-range, real-time, and low-cost camera surveillance， combined with the development status of high-definition analog video， this paper analyzes the main problems of multi-channel high-definition analog video ultra-long-distance transmission based on fiber optic communication technology, such as high cost, slow transmission rate, and poor real-time performance. It proposes a network solution for long-distance transmission of analog video based on 10 gigabit link aggregation, which is a key technology for multi-channel high-bandwidth high-definition analog video transmission over a single optical cable. This solution can help solve the problem of ultra-high-cost transmission over long distances for coaxial analog high-definition video surveillance, and provide an indispensable component for the overall solution of analog monitoring, with a leading role.

Abstract：How to accurately provide high-quality information to users is the critical issue for information retrieval system, which are intended to effectively improve user application experience. Based on the progress of related research at home and abroad, a dynamic evaluation model towards information retrieval system is proposed from dynamic evaluation mechanism of optimal matching between information resource and user requirement. As the main function modules in the dynamic evaluation model, information quality evaluation method, user expectation evaluation method, situation dynamic evaluation method and user experience assessment method are designed in details, and how to determine the weight of each functional module is optimized by genetic algorithm. The simulation results show that the dynamic evaluation model has good “robustness”, which can not only filter the information that does not meet the needs of users, but also effectively present high-quality information to users who need it, and it will significantly improve user application experience of information retrieval.

Abstract： The Integrated Development Environment (IDE) is designed for a multi-core cryptographic instruction coprocessor, including Instruction Set Simulator (ISS), assembler, debugger and other functional modules. It supports software debugging based on assembly language and performance evaluation of cryptographic algorithms. According to the characteristics of the cryptographic algorithm, the simulator of the cryptographic processing engine in the IDE adopts the way of decoding arithmetic instructions in advance to improve the performance of the simulator. On this basis, to meet the requirements of program debugging and algorithm performance evaluation, an instruction level synchronization simulator and a shared data level synchronization simulator are designed using different simulation strategies. The test results show that the speed of the simulation reaches 4.83 MIPS during the algorithm evaluation of the IDE, and the performance evaluation results are consistent with the hardware simulation.

Abstract： The identity-based cryptography algorithm such as SM9, requires a trusted third party key generation center KGC to generate the user′s identity private key, which will be faced with the risks and problems of key escrow and single point failure. This paper proposes a distributed identity-based cryptography key management scheme. Several participants generate partial identity private key to the user, and the user locally generates its own identity private key, avoiding the key escrowing problem. Meanwhile, the data such as identity status and other data can be uploaded to the blockchain. It can be used to decentralize the query of user′s identity and validity, solve the single point failure and trust problem of single KGC, and improve the system availability and security. The results show that the proposed scheme has obvious advantages in terms of efficiency and bandwidth requirements.

Abstract：Moving coil loudspeaker may experience thermal damage such as open circuit, short circuit, and debonding when driven by large signals due to severe heating of the voice coil, resulting in damage to the speaker unit. By establishing a three-dimensional finite element model of a moving coil loudspeaker unit, the steady-state temperature and stress fields of the speaker unit were simulated under large signal driving based on multi physical field coupling, and the simulation results were verified through experiments. The results show that under the action of a constant voltage power amplifier, the overall temperature of the speaker unit first increases and then decreases with the increase of the frequency of the voice coil current. The temperature of the speaker unit reaches its peak at the rated impedance point, and the equivalent stress is concentrated at the connection between the voice coil skeleton, centering support, and diaphragm, which may cause heating faults due to high temperature. At the same time, the impact of thermal damage to the voice coil on the transient temperature field of the speaker unit was analyzed. This result can provide reference for temperature monitoring and failure analysis of moving coil loudspeaker.

Abstract： In view of the huge computational load of the current YOLOv4 algorithm, it is difficult to meet the real-time requirements of the mask wearing detection system, a lightweight detection algorithm (Light-YOLOv4) was proposed. The GhostNet network structure integrating ECA attention mechanism was replaced by the backbone network of YOLOv4 to reduce the number of parameters. Using dilated convolution and SPPF for reference, ASPPFCSPC structure is proposed to replace SPP effectively to increase the receptive field. In order to solve the overlapping problem caused by too dense targets, the RepBox loss function is added on the basis of the original, so that the prediction boxes of different targets are far away from each other to reduce the missed detection. The experiment shows that the mAP value of the Light-YOLOv4 algorithm is 94.2%, FPS is 46.3 frames, and the model size is 95 MB. Compared with the mAP value of YOLOv4 algorithm, the detection rate is only reduced by 1.1%, the detection rate is increased by 51.8%, the number of parameters is reduced by 70.0%, and the model size is reduced by 61.1%, friendly to low performance detection equipment.

Abstract： In software-defined computing architectures, DSP, as a commonly used hardware resource, is bound to develop virtualization in order to maximize its performance. This paper proposes a multi-core DSP context environment backup and resume scheme, with core 0 as the control core, through reasonable memory allocation and read/write operations, the states of remaining core in the calculation process, such as register state, stack state, data state, and program state, are saved and written back, achieved the function of switching from computing task M to computing task N, and then switching back to M after N is completed. Using TI 66AK2H14 to verify its feasibility. This scheme provides practical methods and experience for the flexible application of multi-core DSP hardware resources.

Abstract：Industrial equipment represented by robotic arms directly affects the production level of manufacturing industry. In some situations such as painting and welding, people hope that the trajectory of the robotic arm’s end will meet expectations. Due to different working conditions and external interference, it is difficult to keep the single-axis tracking performance of each joint consistent. At this time, multi-axis synchronous control is required so that multiple motors can cooperate synchronously to complete the work and ensure the accuracy of end trajectory. In this paper, the synchronous correction amount of each joint based on the relative coupling structure is obtained after analyzing the three-dimensional trajectory error and kinematics characteristics of serial manipulator. The effect of the method is verified by a comparative experiment on the six-axis manipulator experimental platform based on Xilinx ZYNQ.

Abstract：When the conventional multi-channel DMA data transmission structure is applied to the multi-sensor connected artificial intelligence platform, with the increase of sensor type and quantity, a lot of FPGA logic and storage resources will be consumed in the process of channel protocol conversion and AXI bus extension, which will easily lead to logic congestion and increase the difficulty of tool routing. At the same time, the closed AXI system lacks the flexibility of channel differential control, and it is difficult to adapt to the multi-mode data transmission requirements of artificial intelligence platform. Therefore, a DMA data transmission structure with AXI bus multiplexing mode is designed, which can greatly reduce the number of AXI buses, reduce FPGA resource consumption and tool routing time, conveniently fit additional logic to realize multi-mode DMA data transmission, and provide a flexible and efficient multi-source data acquisition mechanism for artificial intelligence platform.

Abstract： In order to improve the bandwidth efficiency and system reliability of the data processing module accessing the DDR memory in the image processing system of the infrared thermal imager, a DDR memory access scheme based on AXI4 bus is designed using Xilinx Kintex-7 series FPGA. The user interface design of AXI4 bus is realized, and the requirements for real-time access control of multiple ports of DDR memory are completed. The test results prove that the design is feasible, and the interface conforms to AXI4 bus protocol, so that the read/write bandwidth and efficiency of the data module in the infrared image processing system for DDR can reach a higher level.

Abstract：At present, domestic terminals are gradually becoming the mainstream of China's terminal market, and terminal products based on the PKS (Phytium+Kylin+Security) system, as the main force in China, undertake a more important mission and urgently need to speed up the optimization to meet the needs of various domestic industries. To meet the growing needs of the user group, this paper predicts user function usage scenarios from the user's point of view on the basis of the single-point verification method of functions, and innovatively proposes a terminal function scenario verification method based on the PKS system. By comparing and analyzing the two methods, the verification data of three domestic terminals proves that the efficiency and value of the functional scenario verification method are better than the traditional single-point verification method, which can promote the continuous optimization of domestic terminals and provide new ideas for the domestic terminal verification system.