Abstract：In the field of cloud computing, optimization of resource management and task scheduling is crucial to improving system efficiency and resource utilization. As the industry's leading container orchestration tool, Kubernetes (K8S) is dedicated to the automated deployment, expansion and management of application containers. One of its core advantages is to use efficient scheduling algorithms to achieve cross-cluster deployment and execution of containers. This strategy plays an important role in application system portability, security, optimized resource utilization and integrated deployment, making it more agile and efficient in responding to changing business needs. In view of this, K8S scheduling algorithms have become a hot research topic in the industry. This article aims to comprehensively investigate and analyze K8S-related scheduling algorithms and their actual performance in different application fields, with special attention to three areas: improvement of general scheduling algorithms , artificial intelligence-oriented scheduling strategy and elastic scaling-based scheduling technology. Finally, through comprehensive analysis, the shortcomings of current research and issues that need to be solved in future research are revealed, providing reference for further optimizing the K8S scheduling algorithm.

Abstract：Using active learning models to select the most valuable data points for annotation is one way that deep learning reduces the amount of labeled data required. Prediction loss models are a type of task-agnostic active learning models that perform well across multiple tasks. However, these models are not end-to-end models, and changing input features can lead to input bias during the training of the loss prediction network. This paper proposes a temporal feature fusion prediction loss model to address the issue of input bias in such models. Experiments demonstrate that the method proposed in this paper achieves an average performance improvement of approximately 1.5% across various tasks compared to previous state-of-the-art methods, and an average improvement of 5% compared to the original prediction loss model.

Abstract：Video Synthetic Aperture Radar (ViSAR) systems enable dynamic monitoring of the target area with low latency and high resolution. High performance computing is the key technology of ViSAR system. In order to meet the real-time requirements of ViSAR system, a ViSAR imaging scheme based on Graphics Processing Unit (GPU) is proposed. The scheme deploys the Polar Format Algorithm (PFA) to the GPU. Optimization using multi-stream processing techniques, asynchronous parallelism, etc., which take full advantage of the GPU's computational performance. The results show that the architecture takes 0.17 seconds to process a single 2 048×2 048 size, which is 32.8 times faster than the average acceleration of the Central Processing Unit (CPU). It effectively solves the real-time imaging problem of ViSAR system.

Abstract：Based on the importance of information security and the demand of local technology, in order to improve the autonomy and control of information security technology, this paper will design a security chip applied in the field of information security. The chip takes the state secret SM3 algorithm as the core of the engine, adopts the single-wire communication method, occupies only one IO communication resource, and the protocol supports the 1-wire bus protocol to meet the needs of different application scenarios. The circuit is based on the domestic commercial 110 nm CMOS process line to complete the circuit design and flow chip manufacturing. The chip layout area is 1.2 mm×1.9 mm, and the communication function of the circuit is normal and stable after the flow test and verification. SM3 algorithm engine is highly efficient and fast, the result shows that the properties of this chip are superior.

Abstract：As military UAVs and other avionics systems continue to develop in the direction of miniaturization, intelligence, and integration, how to effectively meet the low SWaP (Size, Weight and Power) requirements of equipment has become a major problem. In this paper, the development of a certain type of broadband integrated digital preprocessing module is introduced, and the signal processing platform (DSP, FPGA, SerDes and DDR chip) is integrated by using the "bare chip + high-density substrate" system-in-package (SiP) method, which replaces the traditional method of "packaging chip + printed board + planar integration" commonly used in the industry, and realizes the high-density integration of broadband integrated digital signal processing module. Under the condition that the main performance indicators (programmable logic resources, fixed-point processing capabilities, floating point processing capabilities, and data transmission rates) remain unchanged, the area of the signal processing module is reduced to 45 mm×45 mm, and the weight is reduced to 103 g.

Abstract：With the development of advanced computing industries such as cloud computing and big data, implementing intelligent management based on hardware management mode is of great significance. A hardware management controller chip is designed and implemented on the RISC-V core, utilizing network communication tools to effectively manage application systems. A verification platform is built on UVM verification methodology for simulation verification, and a chip prototype verification platform is constructed on FPGA for collaborative verification and stability testing with the upper computer. The physical design adopts a 40 nm process with a design frequency of 250 MHz.

Abstract：Electromagnetic relays are widely used in the fields of modern national defense, military, industrial automation and transportation. When the electromagnetic relays fail in the system, the reliable operation of the entire electrical system will be affected. In order to improve the reliability of the electrical system, it is necessary to test the characteristic parameters of the relay to evaluate its working performance and improve its stability. Aiming at the problem of easy failure of electromagnetic relay contact, this paper designs a set of online testing system of electromagnetic relay based on FPGA. The railway relay is used as a sample, the characteristic parameters of the relay are analyzed, and the time parameters which can reflect the degree of contact degradation are selected for testing. This portable online test system, which can be applied to multiple relay models, can detect the waveforms of voltage changes during relay suction and release in real time and store the data. It provides data support for the subsequent performance status evaluation of relays, and also provides reference data for the repair and maintenance of electromagnetic relays.

Abstract：At present acquisition and display of fuel system on domestic helicopter mostly adopts the system integration test, which can not locate the fault quickly and accurately. But based on LabWindows/CVI, the designed and developed test program for fault detection and repair of aircraft fuel system can not only test certain component separately, but also can do system integration test. Through the analysis of serial data, it can quickly locate the fault of fuel signal converter or fuel indicator. This diagnosis method is easy to achieve, and can help to make up the deficiency of fault detection and repair of fuel system at present. This method shows a certain application aspect.

Abstract：The Guessing Random Additive Noise Decoding with Ordered Group Codebook (OGC-GRAND) is proposed to solve the problems of large codebook capacity and slow decoding speed in GRAND. The decoding process can be executed by segmenting the decoding sequence, sorting the code segments according to the code weight of information bits, grouping the code segments according to the code weight value, and generating a codebook for each group. The simulation results show that the decoding speed of the algorithm is twice as fast as that of GRAND, and the bit error rate is the same as the Maximum Likelihood Decoding (MLD), which verifies the effectiveness of the algorithm.

Abstract：In response to the demand for miniaturized ultra-wideband radar systems, a novel ultra-wideband low-profile antenna array is designed with close coupling between antenna elements achieved through a cross-coupling structure. The proposed array antenna unit enhances the traditional Vivaldi antenna structure by introducing a pair of arc-shaped slots with circular cavities, giving it a dipole-like radiation pattern at the top of the Vivaldi antenna. The cross-coupling structure is employed to achieve tight coupling between the antenna elements, significantly reducing the overall profile height of the antenna. Additionally, a dielectric matching layer is introduced on top of the antenna unit to further improve the matching performance. Simulation results demonstrate that the designed array antenna exhibits a standing wave ratio of less than 2 across the 2.6 GHz to 15 GHz frequency range. The maximum gain of the 12×12 antenna array exceeds 20 dB, while the profile height of the array antenna unit is merely 15 mm (0.125 times the low-frequency wavelength). Hence, this antenna design not only meets the requirements of ultra-wideband performance but also greatly reduces the profile height of the antenna, offering significant engineering applications.

Abstract：Regular expression matching technology has significant application value in data governance, parsing extraction, and deep packet inspection. However, due to its low matching performance on general-purpose platforms, it cannot meet the application requirements of real-time data processing in practical environments, which limits its application scope in the field of high-performance data processing. In response to the current issue, a high-performance regular expression matching algorithm based on untrusted character comparison is proposed, which is called ɑFA. This algorithm determines whether a sequence of consecutive characters belongs to the untrusted character set of the most frequently accessed state. By doing so, it acquires the number of characters that can be skipped directly without DFA matching, reduces the number of accesses to the DFA state transition table in memory during character matching, and thus achieves accelerated processing of character matching. The experimental results indicate that the ɑFA algorithm can achieve a performance acceleration of approximately 1.05 times to 7.58 times compared to the original DFA matching algorithm.

Abstract：Visualization tools can improve the complex and tedious work problems in the field of 3D design, but few existing tools take into account dynamic design and low programming threshold requirements at the same time. For the designer group, this paper designs and implements a visualization tool, focusing on dynamic design content in three-dimensional scenes. A dynamic task scheduling algorithm based on task value, influence and urgency is used to improve the response delay problem of key visual effects. Experimental and operational results show that the scheduling algorithm can optimize the execution of key tasks, and the visualization tool helps to design three-dimensional scenes easily and quickly.

Abstract：To address the issue of low model accuracy in practical applications of marine debris identification, this paper proposes an improved garbage classification algorithm based on optimized YOLOv7. In the image enhancement part, a probabilistic UIE framework is introduced to reduce the loss of feature information by incorporating eSE attention. In the loss function part, a two-layer attention mechanism is added to the IoU loss function to enhance the model’s generalization ability when combined with the EIoU loss function. The proposed algorithm is applied to marine debris detection tasks and evaluated on benchmark datasets. The average precision on the YOLOTrashCan datasets achieves 69.5% and 63.5%, respectively, representing a 6% and 1.6% improvement compared to the YOLOv7 algorithm. Overall experimental results demonstrate that the algorithm constructed in this paper effectively enhances the accuracy of marine debris detection.

Abstract：This paper introduces an engineering realization of a Ku-band 800 W GaN high linear solid-state power amplifier. A continuous wave output power of 850 W in 750 MHz operation band is realized by the Gysel power divdider and waveguide based power dividing/combining network with 32 GaN MMIC chips. The RF predistortion linearization technology is used to optimize the linearity of the GaN power amplifier, and the third-order intermodulation of the power amplifier is improved by more than 5 dB, which is better than -32 dBc. The power amplifier adopts a forced air cooling scheme with a heat pipe fin radiator, which improves the heat transfer efficiency of the radiator and has good heat dissipation performance. By monitoring the temperature of the power amplifier chip and automatically configuring the speed of the cooling fan, adaptive thermal management of the power amplifier is achieved, which reduces power consumption while reducing product noise. The power amplifier is equipped with comprehensive control and protection functions and has stable technical status. Two power amplifiers form a 1:1 system, which meets the reliability and practicality requirements for engineering use and is suitable for microwave transmission systems in the fields of measurement and control, communication, broadcasting, and television.

Abstract：To meet the requirements of large instantaneous operating bandwidth and simultaneous multi-beams of the satellite-borne Ka-band phased array antenna, a wideband analog multi-beam phased array antenna based on intra-subarray phase shift and inter-subarray delay is designed. The designed 28×28 unit array is divided into four subarray structures, with phase shifters used for each unit within the subarrays and delay lines used between the subarrays. This combined control scheme of phase shifters and delay lines can achieve wide-band and wide-angle scanning of phased array antennas. The simulated results show that, at an instantaneous operating bandwidth of 800 MHz and a scanning angle of ± 54°, the pointing accuracy deviation of the proposed antenna is no more than 0.4°, and the gain deterioration is no more than 0.5 dB. At the same time, the Antenna-in-Package (AiP) architecture is used to achieve the lightness, thinness, and integration of antennas, which is suitable for the design of wideband multi-beam satellite-borne phased array antennas.

Abstract：Based on the Micro-LED product series, this experimental project has designed an FPGA-based LVDS automatic calibration for the multi-channel video stream transmission system. The system platform is equipped with an external GSV2011 decoding chip, which converts the obtained 2K@120 Hz/4K@60 Hz video stream signals into 80-bit data package according to custom specifications, and then pushes them to the LYDNT27001 constant current source display driver chip. In thise system, the video stream data transmission involves multiple levels of FPGA chip data transfer, utilizing LVDS low-voltage differential transmission technology. In order to adjust the data bit alignment and sampling stability issues with the SerDes, the reference and monitor signals are identified during the process of data stream transmission video stream data of this system transmits through LVDS multiple channels, which can achieve a transmission rate of up to 10 Gb/s. This experimental project demonstrates that the system can operate stably, reliably, and efficiently, therefore it has certain practical value in engineering field.

Abstract：Electrocardiogram (ECG) is a key tool for diagnosing heart-related diseases. The wearable ECG monitor Holter is an important means of out-of-hospital detection. Miniaturization, portability, and real-time detection are the optimization directions. Artificial intelligence technology is used in various fields including electrocardiogram diagnosis, but there are problems such as large number of parameters, difficulty in miniaturization, and slow calculation speed. It does not meet the requirements of portable electrocardiogram monitors, and programmable logic gate devices (Field-Programmable Gate Array, FPGA) has parallel acceleration characteristics. This article developed a BeatNet based on 1D-CNN for ECG diagnosis.

Abstract：The linear array CMOS photodetector sensor possesses advantages such as high sensitivity, a wide spectral response range, low power consumption, and a compact size. It is widely used in the development of portable spectrometers. To address the issue of baseline drift caused by the increasing dark current of the CMOS image sensor, a dynamic baseline compensation system based on FPGA for the spectrometer is designed. The system utilizes reserved pixels on the sensor to calculate the baseline value for each frame in real-time and provide feedback. It employs high-performance operational amplifiers, differential amplifiers for voltage tracking, baseline compensation circuits, and single-ended to differential circuits to process the CMOS analog signals and perform high-speed A/D conversion. A precision DAC chip is used to provide real-time dynamic feedback for baseline compensation values.The final test results demonstrate that as the integration time increases, this design consistently maintains a lower baseline level for spectral data. The system's circuit design is flexible, it ensures accurate spectral data acquisition, and it effectively controls the baseline, making it well-suited for detecting weak spectral signals.

Abstract：In the actual direction finding system, when the weak signal and the strong interference are spatially close, the spatial spectrum direction finding system can only estimate the direction of arrival (DOA) for the strong interference, and the performance of DOA estimation for the weak signal is degraded or even invalid. To address this problem, the spatial spectrum extended noise subspace algorithm combined with channel amplitude-phase error correction is investigated for DOA estimation of weak signals under strong interference suppression conditions. The method de-weights the noise covariance of the sampled signal and corrects the spatial spectrum guidance vector of the spatial spectral expansion noise subspace algorithm. The experimental platform is constructed based on Universal Software Radio Peripheral (USRP) and printed dipole linear antenna array, and the experimental results demonstrate that the spatial spectrum extended noise subspace algorithm combined with the improved channel amplitude-phase error correction method can realize DOA estimation of weak signals while spatial spectrum suppression of neighboring interference sources.

Abstract：Aiming at the key problem of high precision time synchronization between multi-station distributed cooperative stations，the basic principle and accuracy analysis of the two-way satellite time transfer are introduced in detail. A kind of no-center satellite two-way time transfer architecture and time synchronization algorithm are designed. Considering hardware resource constraints and providing redundant time difference measurement data, it avoids the failure of the entire system time synchronization function caused by a station failure，the robustness and flexibility of time synchronization are improved. Based on the PPP（Precise Point Positioning），the time synchronization accuracy of long-range Two-way satellite time transfer if verified，better than 6 ns.