Abstract：Combined with the finite difference time domain, physical optics and ray tracing in inhomogeneous media, the influence of the electric propulsion plume on the electromagnetic transmission environment around the satellite is studied, and the simulation software for the electromagnetic effect of the propulsion plume is developed. Because the algorithm uses a computational framework based both on the low-frequency algorithm and high-frequency algorithm, it can provide a broadband solution for the analysis of such problems. Finally, using C# platform, a convenient operation interface is obtained, which can provide an effective numerical simulation method for the analysis of the local electromagnetic environment of satellite, and make up for some deficiencies in this field.

Abstract：GaN, as the new generation semiconductor material, has much wider forbidden bandwidth, higher breakdown voltage, more excellent thermal stability than Si and GaAs, and thus is widely used in the broadband power amplifier design. Based on two GaN RF dies of CREE company are cascaded and the matching circuit is a mixture of centralized and distributed components, a broadband power amplifier is designed in the 20 MHz～520 MHz frequency by using feedback technology to improve band width, RC parallel network to improve stability and micro-strip hybrid matching circuit. The die model and matching circuit are optimized and debugged by the ADS software. In the 20 MHz～520 MHz frequency band, the saturation output power of this power amplifier is more than 9 W, the gain is more than 29.5 dB, the drain efficiency is higher than 40% and the gain flatness is ±0.7 dB.

Abstract：In order to greatly improve the system capacity in local hotspots, the wireless communication infrastructure that can support high-frequency and wideband operation is required for ultra-dense networking. A 4.8～5.0 GHz three-stage high-gain and large-output power amplifier is designed using GaAs heterojunction bipolar transistor(HBT) process to be targeted for 5G microcells. The pseudo-differential structure is adopted to suppress the influence of ground parasitic inductance, while the conversion between single-ended and differential pairs is completed by off-chip low-loss LC balun. In conjunction with active adaptive bias network and RC negative feedback circuit, meanwhile applying the methods of wideband matching and predistortion compensation, ADS(Advanced Design System) simulations verified that the proposed power amplifier can achieve 35.8 dB power gain with 33.5% peak power-added efficiency at a center frequency of 4.9 GHz, and deliver not less than 35 dBm saturated output power in the operating band, which can meet the requirements of seamless coverage of network signals in typical application scenarios.

Abstract：A mu-zero resonance(MZR) resonator is etched in the patch of a printed monopole antenna. The MZR resonator generates a new resonance. As the MZR resonance is lower than the monopole and the resonances merge with each other, size reduction and bandwidth enhancement were obtained. A prototype was designed and fabricated. The test results show that the impedance bandwidth of the MRZ-Loaded monopole is extend to lower frequency remarkably. Because of the small electric structure of the antenna, the omnidirectional radiation and the beam pointing stability is well guaranteed. A microstrip line based model was built to analyze the MZR resonator antenna.

Abstract：An design of a 5 W solid-state power amplifier in Q band by using antipodal finline-to-microstrip transition was presented.The four-way waveguide T-junction and antipodal finline-to-microstrip is designed and simulated through the high frequency structure simulator(HFSS).The simulation result show that the insert loss of four-way T-junction is less than 0.1 dB and the insert loss of antipodal finline-to-microstrip is less than 0.1 dB. The four-way power combiner/divider is made and test. The test result shows that the insert loss of four-way power combiner/divider is less than 2 dB in the the frequency range of 43.5 GHz~45.5 GHz, and the synthesis efficiency is more than 80%. A 2 Watt level die was selected for the amplifier module and the gold boding wire is connected the die to the microstrip. The test result shows that saturation power is more than 5.7 W,gain is more than 10.5 dB and efficiency is more than 9.5% in the frequency range of 43.5 GHz~45.5 GHz. This structure has a very broad application prospect in the field of millimeter wave power amplifier.

Abstract：As the package price of 5G deployment is reduced in the early stage, a large number of data drops will impact the 4G network traffic.At present, the commonly used network traffic forecasting model pays little attention to the package price factor, let alone the data fallback effect brought by network standard upgrade.In this paper, a traffic prediction model based on package and standard driving model is proposed, and corresponding optimization and capacity expansion schemes are selected according to the traffic prediction.4G traffic prediction and construction scheme analysis based on college scenes are very important to ensure the network advantages of operators.

Abstract：Characterized by complex wireless communication environment, concentrated mobile users and large demand for data services, subway has become the key area covered by 5G network.Combined with 5G network characteristics, this paper analyzes the characteristics and coverage requirements of the wireless communication environment of subway hall/platform and tunnel, and proposes 5G coverage solutions for the newly built and existing subway joint scene.

Abstract：2020 is the year of 5G scale deployment and commercial operation for mobile operators. With the development of major systems of operators towards platform and automation, 5G planning and construction by system platform with cloud computing as carrier, big data as means will effectively assist the rapid implementation of national 5G strategy. First of all, this paper analyzes the overall scheme of 5G site planning based on big data and platform, then analyzes the NR(New Radio) coverage prediction and ability algorithm involved in the scheme in detail, and finally studies the site planning scheme based on the calling of 5G simulation interface.

Abstract：This paper presents the theoretical assessment method and a case study of compliance boundary of human exposure to 5G radio base station. The technical issues related to human exposure to radio frequency electromagnetic fields at 5G frequency band, the determination method of the actual maximum EIRP(time domain average) of 5G base stations, theoretical evaluation calculation formulas and evaluation procedures, etc.，are discussed for the assessment of the electromagnetic environment in real scenarios.

Abstract：In order to meet the business requirements of 5G three scenarios, edge computing technology based on network function virtualization comes into being. Operators should follow the trend of the industry, layout edge computing, which is of great significance to the revitalization of datacenter resources, cloud network collaborative operation. Based on the demand and value of 5G edge calculation, this paper proposes the planning and deployment method of 5G edge datacenter from two aspects of business and cost respectively, and meanwhile puts forward the requirements for the configuration of infrastructure such as power supply and air conditioning in the datacenter.

Abstract：As a new generation of information technology, cloud computing based on diverse data and powerful computing capabilities. It integrates some advanced technical practices, and some self-adaption business systems are achieved. From the perspective of data, this paper developed multi-level comparative research on data centers, and summarized the current research and application of cloud computing. Besides an overview of key technologies such as virtualized technology, distributed computing models, massive data storage and management technologies, this paper proposed a method for analyzing cloud computing applications based on data sources, which are divided into internet clouds, industrial clouds, special field clouds. And this paper focused on the corresponding architecture and application features. Finally, the next research directions are provided and this could be helpful for cloud computing related research.

Abstract：The high-performance chip design has a larger design scale, higher frequency, more complex design data and reliability, and more signoff indicators under 7 nm and higher process nodes. Machine learning has been successfully applied in many fields, and complex chip design is a good field for applying machine learning. Cadence built the algorithm into the Innovus tool, and built the machine learning model by learning and modeling the chip design data to improve chip performance. A physical design process that applies machine learning to optimize latency is established to improve chip design performance. This paper presents a machining-learning-based physical design flow that optimizes delay to improve chip design performance. In orde to choose a better solution，the effect of optimizing the cell delay，net delay，cell and net delay separately on the design was discussed and analyisised in detail. Finally，the solution is applied to another block design with more difficult design and higher performance requirements . To verifies the consistency of the flow，a more comprehensive analysis is completed from the aspects of timing，power，wire length，etc.

Abstract：In advanced process node, as the design scale becomes larger and larger, the clock frequency becomes higher and the clock structure becomes more and more complicated, it is increasingly found that the closure of the design depends more and more on the clock quality. For complicated clock structures such as multi-input dynamic mux, IP modules with multiple internal output clocks, etc., the clock structure is analyzed, and the clock structure is extracted from the netlist based on the Innovus tool, clock spec will be updated based on these analysis. At the same time, CTS is performed on an ultra-large 16 nm top design based on the optimized clock spec, combined with the multi-tap clock tree methodology. From the results obtained, it can be found that the run time, clock latency and other aspects have been greatly improved. It can meet the requirements such as the clock length required by the project, and effectively avoid the timing conflict of the block interface.

Abstract：Cadence publicized a new simulator SpectreX which can speed up and keep accuracy in 2019. This article introduces the theory and usage of SpectreX firstly, then focuses on how can use SpectreX to simulate ADLL, compare and analyze the simulation results.

Abstract：With the rapid development of the Internet, the 5G era has arrived and the data transmission rate is getting higher, which is a new challenge to the server research. The memory development has upgraded from DDR3 to DDR4, its operating voltage has reduced to 1.2 V, and the rising edge of the DDR4 signal has dropped to 100 picoseconds. In order to ensure the transmission rate and accuracy of the signal, the crosstalk on the DDR4 transmission line cannot be ignored. This paper adopts the DDR4 transmission line on the motherboard of the server project. Firstly, different motherboard stack models have been designed, and different stackups are used to change the remote reference layer of DDR4. Then the experiment result under different stackups through simulation by Sigrity tools and actual testing has been analyzed. The result shows that the far reference to the 12 V power plane will cause crosstalk of more than tens of millivolts to the DDR4 signal. After adding the ground plane shield between the 12 V power layer and the signal layer, the crosstalk voltage is significantly reduced.

Abstract：In a multi-core SoC system, different processor cores perform a large amount of data read and write operations on memory space and device space. Maintaining cache coherence is facing severe challenges. The verification environment focused on the control flow has been very complicated, and the verification including data correctness check is more difficult due to the complicated control process and large amount of data. In response to this problem, this paper is based on Cadence CHI VIP, AXI VIP and IVD VIP to achieve system-level data coherence verification in a multi-core environment. In this paper, CHI VIP is used to issue a memory access request through the CHI protocol conversion bridge developed by the author, and AXI VIP is used to collect data that arrives in the main memory, real-time analysis and comparison of the request data of the CHI port and the access data of the AXI port by the IVD VIP，to realize stimulus generation and response inspection at a higher level of abstraction. The verification platform can perform data consistency verification at the subsystem level and system level, and has the advantages of rapid verification environment construction and complete coverage of function points.

Abstract：An on-chip temperature sensor based on 0.13 μm CMOS IC process was presented. The core analog circuit and the principle of temperature sensing were analyzed. Slope compensation of reference voltage was used to obtain more sensing accuracy. The temperature sensor was fabricated, and test results showed that, in the range of -55 ℃ to 125 ℃, the sensed temperature was basically in agreement with the actual temperature.

Abstract：The PCIe interface is a kind of high-speed interface widely used on system on chip(SoC). In the register transfer level(RTL) design and development stage of the SoC, it is particularly important to verify the design of the PCIe interface. Different verification platforms are needed to ensure the functional correctness and performance stability of the design. This paper focuses on the method of PCIe interface verification platform based on Cadence emulator, and realizes the verification method with a chip. The practice shows that this method can quickly build the verification platform, provide high emulation performance, support a variety of debugging methods, and effectively complete the verification objectives.

Abstract：A three-channel single-line transmission LED constant current driver chip is designed. The chip has three PWM driver ports to achieve 256-level grayscale output. The key circuit integrated in the chip includes three parts, a data extraction circuit, a data processing circuit, and a lower-level data reconstruction circuit. During cascade work, the first chip performs data extraction and processing on multiple sets of input data streams, retains the first set of data, sends it to the driver port after processing, and simultaneously transfers the remaining data to the next chip correctly. After simulation , the chip has stable transmission characteristics at a transmission rate of 800 kb/s.

Abstract：This paper introduces the low cost of 1 Gb/s source-synchronous SerDes interface application principle, and how to interface low-end FPGA with high-speed data and how to implement a reliable sampling solution for 1 Gb/s data are described in detail. This interface is suitable for source-synchronous SerDes data converter as AD9653. Coupled with application of the low-end Spartan-6 series FPGA，this solution can greatly reduce the cost of data acquisition system, power consumption and complexity.

Abstract：In view of the complexity and huge system of UHF(ultra-high frequency) telemetry ground station of conventional micro/nano satellite，a simple ground receiving scheme using AD9361 is designed. The equipment is composed of RF front-end, baseband processing and upper computer. Through the analysis of RF chain and sensitivity, the feasibility of the scheme is ensured theoretically. Through the experiment of the analog signal source receiving, the results show that the scheme of the UHF receiving equipment is feasible and has been applied in the micro/nano satellite signal receiving test.

Abstract：Mobile Edge Computing(MEC) provides its users with low energy consumption and low latency by providing IT service environment and cloud computing capabilities at the edge of mobile networks. This paper addresses the computing tasks offloading in a single-cell MEC scenario, and designs the optimization function of system total cost, and proposes a joint optimization problem of offloading decision and resource allocation. Firstly, the adaptive genetic algorithm is used to make the offloading decision and subsequent update operations. Based on updating the offloading decision, the two sub-problems of power allocation and computing resource allocation are solved correspondingly. The binary search method and the Lagrange multiplier method are used to obtain the optimal solutions for power allocation and computation resource allocation, respectively. Simulation results show that the proposed scheme can meet the goal of minimizing total system overhead for users under the requirement of delay constraints, and effectively improve system performance and user service quality.

Abstract：The vulnerability of the S7 protocol in the communication process makes the industrial production communication process vulnerable to attacks, causing great security risks. To solve this problem, this paper proposes a method for detecting abnormal traffic of the S7 protocol based on SIMI. Firstly, the characteristics and vulnerability of the S7 protocol are analyzed. Then, a real-time abnormal traffic detection method of the S7 protocol based on SIMI is proposed. Based on the correlation analysis of traffic status characteristics, this method uses the classification characteristics of the SIMI algorithm to effectively identify and classify the real-time status of abnormal traffic in the S7 protocol, and build a knowledge map of the abnormal traffic status of the S7 protocol. Finally, the validity of the method is verified by simulation experiments. Through analysis, the computational complexity of the algorithm is significantly reduced.

Abstract：To solve the security and trust issues in the centralized management, an architecture of digital movie mobile playing system based on blockchain technology is proposed, which provides the credibility and traceability of data by the decentralized consensus mechanism of blockchain and the distributed storage mechanism of IPFS. Here, smart contracts are used to realize the execution logic for the specific functions in the movie mobile playing, including film trading, authorization certification, screening supervision, etc., which integrate the data storage and address record, and reach distributed consensuses among copyright owners, cinemas, projection teams, digital program management centers and regulatory departments. This automatically execution with efficiency and accuracy reduces the artificial intervention in transactions and authorizations, and therefore the fully controllable operation of mobile playing is guaranteed.

Abstract：This paper presents a multi-target tracking system based on terrestrial mobile platform. The system will use some external parameters of the camera on the mobile platform to construct the ground raster map corresponding to the video stream. The system will use HOG algorithm to detect the target and calculate the occupancy of the ground in the raster map to track the target. In order to guarantee the robustness of multi-target tracking under mobile platform, we also propose a target estimation algorithm based on the change of vanishing point in video sequence. By comparing the results of other algorithms in the same video sequence, it is found that the proposed algorithm is effective.

Abstract：Since the angle and the force of the derrick are easy to excess the threshold, inner suspension & inner backstay(ISIB) for power tower always result in fall. Here, the monitoring system of the angle and force is designed by interned of things to improve the ISIB safety, including perception layer of angle and stress by x-y axis tilt angle sensor and stress sensor, ZigBee wireless network to sending the datum to local monitoring system, and 5G network to send monitoring datum from monitoring system to provincial safety monitoring system. This system can check the dip angle of the derrick and the force in real time, to improve the production safety and efficiency of ISIB.

Abstract：Aiming at the problems in the present industrial field HD-SDI test such as the test environment building complex, high cost, SDI transmission characteristics measurement is difficult, this paper designs and develops a multi-channel HD-SDI test system based on FPGA.Firstly, the image data stored in SD card is read through FPGA, and then the data is cached in DDR3.Finally, it is sent to external SDI serializer and SDI cable driver after FPGA analysis and processing, so as to achieve the output of multi-channel HD-SDI standard image. The experimental results show that the test system meets the standard and requirements of HD-SDI transmission protocol, and can be used to simulate the test environment and calibration site in different scenarios, and has the advantages of simple operation and wide practicality.

Abstract：In order to ensure the accurate release of the test site information, avoid the unfairness caused by the time synchronization in the test room，a synchronization information receiving terminal for large-scale examinations is designed based on digital multimedia broadcasting technology. Based on FPGA and MCU design, the terminal can receive DMB signals and drive LED dot matrix screen to display time and test text information in real time, and provides voice broadcast function. The time can be accurately synchronized to the second, and all the test field errors are less than 0.5 s. The displayed test field instructions have the characteristics of synchronization, consistency, accuracy and eye-catching, which effectively guarantees the simultaneous release of time and instructions in each examination room.

Abstract：The signal processing platform usually uses FPGA+DSP+ARM architecture to achieve specific signal processing functions, with the development of signal processing technology, more and more engineering applications require signal processing platform to have dynamic reconfiguration capacity. This paper introduced a design of dynamic reconfiguration based on Ethernet, which can realized the dynamic update of multiple FPGA and DSP on the signal processing platform. At the same time, it did not need the configuration memory in previous design, and the configuration time is short, which can meet the application requirements in various scenarios. The design has been verified in many practical projects, and has achieved ideal experimental results, with high portability and scalability.

Abstract：In order to solve the limitation of multi system FPGA remote update, a design method of multi-system FPGA remote update system based on SoC is proposed. Ethernet protocol is applied to realize the information interaction between the upper computer and SoC control system, and SoC chip controls the loading process to realize the remote update of multi system FPGA. The feasibility and correctness of the new method are verified by practical test. It effectively solves the shortcomings of traditional updating methods, such as complex operation, short distance and long time, and has great significance for engineering application.