Abstract：In order to optimize and upgrade radar display technology, a radar A-display circuit based on FPGA is designed and implemented in this paper. The FPGA integrated radar display IP core is used to realize the sampling, processing and displaying of radar front-end signals. The design takes advantage of the huge programmable logic unit of the FPGA chip. The rich mature IP cores realize the functions of receiving, sampling, transforming and displaying the radar input signal of the single-chip logic chip. It simplified the hardware structure of the previous radar display system, reduced the display delay of the signal, and improved the radar display performance. At the same time, the design can realize other radar display methods by further modifying the internal IP core, so that it has the versatility and scalability of hardware devices.

Abstract：Aiming at solving the problem that the traditional electrical direction finding technology cannot meet the requirements of future electronic reconnaissance systems, a microwave photonic direction finding compact system based on phase interferometer principle is proposed and studied by simulation in this paper, using the double parallel Mach-Zehnder(DP-MZM) modulator to realize direction finding with ultra-wide band and high accuracy. The simulation and experiment results show that the proposed system can achieve the phase difference measurement from -90° to 90° in the frequency range of 5~40 GHz, and the measuring error is within ±2°.

Abstract：The noise and interference are usually described by Gaussian distribution in the traditional track association model, while the massive use of electronic equipment makes the battlefield electromagnetic environment more and more complex. To address this problem, this paper proposes a multi-target trajectory association model based on uncertainty distribution, by introducing uncertainty distribution function to describe the noise and interference in the trajectory association process, so that the model is more in line with the real situation on the battlefield, constructs a multi-target trajectory association process in the case of dual sensors, and uses classical algorithms to simulate and verify different numbers of targets. The results show that the model proposed in this paper outperforms the traditional model under the same conditions and can bring improvement in the association accuracy.

Abstract：Small size, low power consumption and low probability of intercept are the characteristics of frequency modulation continuous wave(FMCW) radar. It is widely used in vehicle navigation radar, low probability of intercept radar and so on. In this paper, the system draws on the design of the MIT coffee can radar, a small S-BAND FMCW radar system is developed which draws on the design of the MIT coffee can radar and uses the modularized integrated microwave device. The system designs simple array antenna to increase the echo intensity, adjusts electronic circuit boards to enhance system stability, improves audio interface to make the system more widely used and uses Range Doppler(RD) algorithm to measure target velocity. Furthermore, a modified RD imaging algorithm was implemented to the original stop-and-go static model to compensate for the effect of Doppler stretching on synthetic aperture radar(SAR) imaging during motion. The simulation and experiment results show that the system is reasonable and reliable.

Abstract：In the process of radar to sea detection, the near-range sea clutter echo power is high, which seriously affects the radar receiver work and subsequent signal processing. In order to balance the gain and sensitivity of radar receiver, a reasonable design of sensitivity time control (STC) curve is needed. This paper introduces four STC design curve methods using GARCH model, polynomial function, radar distance equation and exponential function, and compares and analyzes the near-range sea clutter suppression performance of the four STC curves by using the measured data under high and low sea conditions. The experimental results show that the STC curves in the form of radar distance equation have significant performance in suppressing sea clutter in both high and low sea states; the STC curves modeled by GARCH model are suitable for low sea states; the STC curves in the form of polynomial and exponential are close to each other in different sea states.

Abstract：A review of polarimetric Synthetic Aperture Radar(SAR) image classification technology is provided. Firstly, the application value of the classification is discussed, and the technical problems to be solve are proposed. Secondly, the general work flow for polarimetric SAR image classification algorithm is analysed. Thirdly, the domestic and foreign research status and main technical characteristics are compared, emphatically the polarimetric SAR image intelligent classification algorithm based on deep learning theory is summarized. Finally, combined with the development trend of SAR remote sensing，the further study directions of polarimetric SAR image intelligent classification technology are pointed out.

Abstract：With the rapid development of Internet of Vehicular, more and more vehicles′ applications are computation-intensive and delay-sensitive. Resource-constrained vehicles cannot provide the required amount of computation and storage resources for these applications. Edge computing(EC) is expected to be a promising solution to meet the demand of low latency by providing computation and storage resources to vehicles at the network edge. This computing paradigm of offloading tasks to the edge servers can not only overcome the restrictions of limited capacity on vehicles，but also avoid the high latency caused by offloading tasks to the remote cloud. In this paper, an efficient task offloading algorithm based on deep reinforcement learning is proposed to minimize the average completion time of applications. Firstly, the multi-task offloading strategy problem is formalized as an optimization problem. Secondly, a deep reinforcement learning is leveraged to obtain an optimized offloading strategies with the lowest completion time. Finally, the experimental results show that the performance of the proposed algorithm is better than other baselines.

Abstract：Recently, the functions and features implemented on Analog/RF ICs increases greatly which requires much more circuit blocks to be integrated into one single chip. On the other hand, with advanced node processes adopted, the post-layout netlist size of a single circuit block increases sharply. All of these pose a high demand on performance and efficiency of post-layout simulations and debugs. Except on adopt advanced Full-SPICE simulators, like Cadence Spectre X, to speed-up post-layout simulations, the choice and optimization method on post-layout input for simulator is another efficient methodology to speed-up overall post-layout verifications. This paper mainly focused on introducing a new post-layout simulation speed-up flow provided by Cadence Quantus SmartView and ADE Assembler with Spectre X,also comparisons with traditional flows are presented.

Abstract：Compared with simulation verification, the formal verification method can traverse all possible incentives in a short time, which greatly improves the efficiency of verification. The sequence preserving module is closely related to timing control and pipeline control, with large design scale and high logic complexity. This paper introduces the process of verifying the sequence preserving module using formal FPV, and analyzes the JasperGold debug results. Formal FPV verification can improve the verification efficiency and accelerate the verification convergence speed.

Abstract：Power as one part of PPA(Performance, Power and Area) becomes more and more important in large SoC chips, especially under 7 nm technology. AI chips schedule multi-cores in parallel for specific application scenario, which lead to very large power consumption. Power optimization for each core is highest priority for an AI chip design. With a typical power scenario or multi-scenario grouped together, we can do power optimization from RTL synthesis to GDS. The basic flow is using Joules-replay to convert RTL activity file(time-based formats-VCD/FSDB/SHM/PHY) to gate level activity file. Synthesis with Genus has 3 steps: syn-gen, syn-map and syn-opt, Joules-replay is added after each step, and the replayed activity file will be used in power optimization in next step, which increase power estimation accuracy. Innovus place and route also has 3 main steps: place-opt, CTS-opt and route-opt, same flow with Joules-replay can be involved after each step, and it generates stimulus activity for next step. At final timing signoff stage, we use post-sim activity for power opt in Tempus. With this full flow power optimization flow, we can achieve more than 10% power reduction, combined with MBFF(Multi-Bit Flip-Flop) optimization, we can get 21% power reduction finally.

Abstract：At the advanced process nodes(7 nm，5 nm and belows), circuit aging has become a neck problem that restricts chip performance and reliability. The aging effects may cause increasing cell delay, and thus led to the risk of path timing violation. The IC design engineers need to predict the aging timing in the timing analysis and set some aging margin accordingly to ensure the reliable operation of the chip during the service life-time. In view of this, this paper introduces an advanced aging-aware STA solution based on Liberate+Tempus. Evaluation results show that this solution can release the over-designed time margin while keeping the analysis efficiency, the accuracy, as well as the multi-situation analysis capability, thus providing a powerful basis for achieving advanced chip design with higher reliability and better performance.

Abstract：In this paper, Cadence 3DIC Integrity and ICLEAGUE HITOC Design Kit are used to implement the back-end of 3DIC logic stack logic chip. In the project, the separation, distribution, definition and other aspects of proto seeds(i.e., minimum distribution unit) in Cadence 3DIC Integrity were studied and optimized. In addition, the paper provided an algorithm of routing arrangement between the top-level power planning and Hybrid Bonding bump，which is optimized to obtain as many Hybrid Bonding bumps as possible and also keep the strength of the power network, thus increasing the number of ports between top die and bottom die. The final results of this paper show that compared with PPA(performance, power consumption and area)implemented by traditional 2D chips, the experiment has achieved 12% increase in frequency, 11.2% reduction in area and 2.5% reduction in power consumption.

Abstract：In this paper, an aging standard cell library considering both BTI(Bias Temperatrure Instability) and HCI(Hot Carrier Injection) is obtained by an advanced characterization method based on Cadence Liberate + Tempus solution, which can be used by Tempus to perform Aging-aware Static Timing Analysis(Aging-aware STA). Compared to setting a flat derate to the circuit, the aging library indicates the timing information of a certain range of aging stress conditions for different arcs of different cells, which optimizes PPA(Performance/Power/Area)of the circuit. In addition, only one library is invoked making STA simpler and easier to operate.

Abstract：With the rise of industries such as big data, artificial intelligence and 5G, there is a huge demand for high-speed computation, high-speed interface and low-power chip solutions. Therefore, advanced packaging, which plays a significant role in the continuation of Moore′s Law, including 2.5D and 3D packaging technology, has become an important topic in the semiconductor industry. The main difference between the 2.5D advanced packaging and the traditional 2D packaging is that there is an extra layer of silicon interposer, which uses the thin metal line width and fine metal spacing capabilities of the silicon process to achieve high density interconnection. This article described a design flow implemented with Cadence 3D-IC platform by which a 2.5D packaging interposer design is developed on Globalfoundries 65nm technology process. HBM2e 3.2 Gb/s high speed interconnect on a 3-Metal-Interposer is achieved and verified by signal and power integrity simulation and analysis making this product has both performance and cost advantages.

Abstract：Aiming at the problem of time-consuming and lengthy problems caused by tedious manual operation in the traditional display audio test process, this paper combines the basic principles of display audio test to propose a display audio automatic test system based on virtual instrument technology. The program designs the communication circuit between the PC and the display to be tested, and realizes remote communication through the mixed programming of LabVIEW and VC++. Then, the control of the measuring instrument is realized through the related tools of the virtual instrument. Finally, combined with the audio test steps，the system test process is designed to realize the automatic execution of the full test project. Experimental verification shows that compared with manual operation, the system has a higher degree of automation under the same accuracy, and the average test time is shortened by 84.25%, which provides a practical reference scheme for automatic audio testing of display devices.

Abstract：In the measurement test of unsteady load on helicopter rotor surface, the performance of slip ring and the electromagnetic radiation of the field environment have great influence on the quality of external clock signal. In some serious cases, the affected external clock signal may lead to erroneous acquisition actions, which makes it impossible to accurately obtain the load data at a specific azimuth. In order to improve the quality of the external clock signal, a wireless clock jitter estimation and correction method of data acquisition system in rotating environment is proposed. The external clock signal is transmitted through the wireless transceiver modules, two sets of triangular waves with the phase difference of 90° are used to estimate the clock jitter with equal amplitude hypotenuse, and the Lagrange interpolation algorithm is used to correct the samples of sensors. Simulation and wind tunnel tests show that this method can effectively reduce the acquisition error caused by external clock jitter, and has significant effect on accurately measuring the load signal on the rotor surface in rotating environment.

Abstract：The aging and damage of the power line and the loose connection will cause a fault arc, which may accidentally cause a serious electrical fire. There are differences in arc faults caused by different types of loads, which makes it difficult to identify arc faults in residential areas. This paper presents a method of series fault arc recognition based on time-frequency diagram and deep convolutional neural network. Through the arc fault experiment, the current data of the normal load and the fault arc are collected. The single load half-cycle current data will be converted into three-dimensional feature images through continuous wavelet transform(CWT), and then these images will be input into the improved convolutional neural network(CNN) for training and testing. The experimental results show that the accuracy of identifying the normal and arc status of a single load is above 99.31%，the accuracy of identifying the working status of multiple loads can reach 99.2% on average.

Abstract：In the generalized frequency division multiplexing system(GFDM), in order to solve the problem of severe signal distortion in the sub-6 GHz frequency band channel of the vehicle-mounted mobile communication under the 5G network, an adaptive equalizer based on high order long short-term memory(HO-LSTM) neural network structure is proposed. Based on the traditional high-order feedforward neural network(HO-FNN), HO-LSTM adaptive equalizer uses the generalized memory polynomial model(GMP) with lower complexity instead of Volterra model, and introduces LSTM neural network to make it more suitable for the prediction of complex nonlinear models. The results show that, compared with the traditional HO-FNN equalizer and LSTM equalizer, the equalization effect of the proposed HO-LSTM equalizer is significantly improved, and the system performance is further improved.

Abstract：In order to ensure the efficiency of signal synthesis between multiple channels in a digital phased array, the system needs to provide highly stable time-frequency signals for multiple sub-arrays of the phased array. There is a problem of poor amplitude and phase consistency in the method that the traditional phased array uses cables to directly distribute and transmit. In this paper, a time-frequency signal distribution and transmission technology based on optical fiber wavelength division multiplexing is proposed, which can effectively solve the problem of efficient and stable distribution and transmission of time-frequency signals in digital phased arrays. The amplitude of each branch signal after distribution and transmission varies with temperature within ±0.5 dBm, and the phase varies with temperature within ±3°. The time-frequency signal distribution and transmission technology has been successfully applied to a digital phased array multi-target unified measurement and control system.

Abstract：Aiming at the needs of satellite transceivers, a dual-band, dual-port, dual-antenna common-aperture microstrip antenna was designed. Both antennas work in the main mode by the radiation patch loading short via technology, with the external square patch and the internal circular patch corner cutting technology. Dual antennas work in common aperture, radiating left-handed circular polarization(LHCP) and right-handed circular polarization(RHCP) waves respectively, the complexity of the satellite dual antenna layout is reduced effectively. The simulation results show that the antenna has a return loss of -13 dB at the frequency of 1.615 GHz, the 10 dB bandwidth of 50 MHz, the gain of 6 dB, the half-power beam width of 90°, and the ±60° beam axis ratio less than 3 dB；the antenna has a return loss of -18 dB at the frequency of 2.491 GHz, the 10 dB bandwidth of 40 MHz, the gain of 6 dB, the half-power beam width of 90°, and the ±60° beam axis ratio less than 3 dB；the dual-port isolation is better than 32 dB. After processing, the actual measurement results are consistent with the simulation results, and the antenna has certain guiding significance for the design of dual-band, dual-port common-aperture antennas on satellites.

Abstract：Non-intrusive load decomposition can decompose the electricity consumption information of each consumer from the current change information of the main meter, which is convenient for providing electricity consumers with more refined and targeted electricity management and dispatching services. The current non-intrusive load decomposition algorithm using one-dimensional convolution has the problems that the decomposition accuracy is not high, the new user appliances need to be retrained, and the complexity is high. Based on this, this paper uses the effective value of current and the harmonic component information after Fourier transform to propose a load decomposition algorithm based on one-dimensional convolutional neural network, which uses similarity comparison to decompose the current information of each consumer, and solves the new problem that increasing users or using electrical appliances requires retraining. It is found through experiments that the method proposed in this paper can also improve the accuracy of load decomposition to a certain extent, and the complexity is low.

Abstract：Effectively detecting discriminative local areas and more accurately extracting fine-grained features of images will help improve the classification effect of fine-grained images. For this reason, a fine-grained image classification method combining dual attention mechanism and multi-region detection is proposed. Multi-region detection aims to locate discriminative image regions through class label learning, and then extract the features of the discriminative local regions through a feature extraction network and merge them with global features. Similarly, a more precise feature extraction network can extract fine-grained features of an image. Therefore, by combining the dual attention mechanism and multi-region detection, the proposed method respectively achieves 88.3%, 94.5% and 92.3% accuracy on three public fine-grained image datasets, CUB-200-2011, StanfordCars and FGVC Aircraft.

Abstract：Wind energy is the most widely used renewable energy. Accurate wind speed prediction is critical for the safety and stability of wind power system. Besides traditional numerical weather prediction, the machine learning technique has been used in wind speed prediction of different time scales. However, most previous studies focused on the wind speed sequence of single station and ignored the spatial dependency and correlation of wind. To improve the prediction with spatial information, this paper tries to extract the wind spatial correlation features in one region area and reconstruct the wind speed using deep belief network(DBN). The experiment results of different regions prove that the spatial deep belief network can reduce the prediction error significantly and increase the accuracy of wind speed prediction by 0.4 m/s on average.

Abstract：Mobile applications need to store and access more and more data, and the storage space of mobile devices is limited, it is difficult to meet the needs of users. When developing mobile applications, the selection of appropriate and efficient data storage and access mechanism is widely concerned. In view of the four data storage and access mechanisms provided by Google′s Flutter cross- platform mobile development framework, such as key-value pair, File files, SQLite database and network, this paper explains their inner working principles in depth, and gives the specific implementation methods and implementation codes. Finally, according to the characteristics of the four data storage access mechanisms and the actual application development requirements, the application scenarios of each mechanism are analyzed.

Abstract：In recent years, with the rapid development of field science and technology and its wide application in military field, relevant professional training will be reformed accordingly. The application fields such as professional knowledge, new technology platform and system integration will also be greatly enhanced. As the content of training increases day by day, there is an inevitable trend of increasing content and difficulty of training. In actual scenarios, due to the site, equipment, equipment and other reasons, relevant business training and the whole process of all elements of the drill cannot be carried out. Therefore, it is necessary to adopt brand-new scientific and technological means, through the combination of virtual and practical, the combination of training and assessment and so on. Through virtual and real interaction technology, the operation flexibility, convenience and ease of use of training mode are obvious, and it also brings more secure and reliable technical support for the research and development of new technology and equipment. The platform makes full use of simulation training deployment, simulation service deployment and other methods to realize the application of elements in the whole process of military operational training and drill through network, control, simulation, photoelectric and other technologies，to standardize training content, improve training quality, strengthen training effect, measure training level and test training results.

Abstract：This paper analyzed the principle of driver protection technology of solid state power controller based on voltage comparator, and the protection circuit of decreasing gate-voltage was designed. The protection circuit of decreasing gate-voltage by setting output voltage value and voltage rise/fall speed, realized the MOSFET gate voltage control, and the load in over-current or short-circuit protection function. The proposed method solved the existing problem using voltage regulator diode to judge the over-current threshold voltage, which lead to the control precision of MOSFET gate voltage is not high and protected MOSFET repeatedly open/close within a time delay. The analysis and simulation on the circuit has been made, and the results show that the protection circuit of decreasing gate-voltage can protect short-circuit load within 45 μs.

Abstract：The paper is introducing the surge suppression circuit of a star sensor briefly. According to the design methods existing of surge suppression circuit, a component parameter analysis and calculation method with the best circuit performance is proposed. Starting with the stable realization of the circuit function and the electromagnetic compatibility of the circuit, this paper analyzes the selection and analysis of the key devices in the surge suppression circuit. Through theoretical analysis and experimental simulation, it is proved that the device selection obtained by the compatibility analysis idea proposed in this paper is effective and correct under the given design conditions. At the same time, it provides a reference for the surge suppression design of other subsystems, so as to improve the reliability of the whole on-board electronic equipment.

Abstract：The analog front-end of traditional navigation receiver based on superheterodyne or low IF is complex in function, high in power consumption and not conductive to monolithic integration. Based on the idea of analog minimization and digital maximization, a novel analog front-end of navigation receiver based on software radio architecture is designed and implemented by integrating a high gain RF amplifier, a high speed low power ADC and a low jitter clock phase-locked loop. Through 55 nm CMOS process circuit design, layout design, simulation and silicon wafer verification, the test results show that the analog front-end of navigation receiver works normally and only one analog receiver channel is able to process the multimode navigation signals which greatly reduces the size and power consumption of analog circuit. The analog front-end circuit has successfully applied in a multimode navigation SoC chip.

Abstract：The TT&C system usually use calibration tower，radio star or geostationary satellite for G/T measurement.Now our country build a group of TT&C systems for the data reception of low earth orbit Ka-band satellites.The size of these antennas ie 12 meter in diameter.Most of these TT&C systems can not use conventional methods for G/T measurement.At the same time,general formula can not meet the accuracy requitement for Ka-band G/T calculation.To solve the problem,this paper gave a formula and solution with drone for Ka-band G/T calculation.Under the method,this paper analyzed and calculated the effects of atmospheric attenution，positioning accuracy of drone，radio beacon′s signal amplitude variation and antenna′s pointing accuracy.The effectiveness of this method was verified in a proving ground.The method sovles the problem that most TT&C systems can not measure G/T at Ka-band.